AD6636PCB datasheet(28/72 Pages) AD

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AD6636

Rev. 0 | Page 28 of 72

Amplitude Dither

Amplitude dither can be used to improve spurious performance

of the NCO. Amplitude dither is enabled by writing Logic 1 in

the amplitude dither enable bit of the NCO control register of

the channel under consideration. Random amplitude is added

to the LSBs of the sine and cosine amplitudes, when this feature

is enabled. Amplitude dither improves performance by

randomizing the amplitude quantization errors within the

angular-to-Cartesian conversion of the NCO. This option

might reduce spurs at the expense of a slightly raised noise

floor. Amplitude dither and phase dither can be used together,

separately, or not at all.

NCO Frequency Hold-Off Register

When the NCO frequency registers are written by the

microport or serial port, data is passed to a shadow register.

Data can be moved to the main registers when the channel

comes out of sleep mode, or when a sync hop occurs. In either

event, a counter can be loaded with the NCO frequency hold-

off register value. The 16-bit unsigned integer counter starts

counting down, clocked by the input port clock selected at the

crossbar mux. When the counter reaches 0, the new frequency

value in the shadow register is written to the NCO frequency

frequency register as soon as the start sync or hop sync occurs.

See the Chip Synchronization section for details.

Phase Offset

The phase offset register can be written with a value that is

added as an offset to the phase accumulator of the NCO. This

16-bit register is interpreted as a 16-bit unsigned integer. A

0x0000 in this register corresponds to a 0 radian offset and a

0xFFFF corresponds to an offset of 2π × (1 − 1/216) radians.

This register allows multiple NCOs (multiple channels) to be

synchronized to produce complex sinusoids with a known and

steady phase difference.

Hop Sync

A hop sync should be issued to the channel, when the channel’s

NCO frequency needs to be changed from one frequency to a

different frequency. This feature is discussed in detail in the

Chip Synchronization section.

FIFTH-ORDER CIC FILTER

The signal processing stage immediately after the NCO is a CIC

filter stage. This stage implements a fixed-coefficient,

decimating, cascade integrated comb filter. The input rate to this

filter is the same as the data rate at the input port; the output

rate from this stage is dependent on the decimation factor.

cic

CIC

The decimation ratio, MCIC, can be programmed from 2 to 32

(only integer values). The 5-bit word in the CIC decimation

of one less than the decimation factor is written into this

the CIC filter stage. The frequency response of the filter is given

by the following equations. The gain and pass-band droop of

the CIC should be calculated by these equations. Both parame-

ters can be offset in the RCF stage.

)

(

)

(

⎟

⎠

⎞

⎜

⎝

⎛

−

CIC

)

(

SIN

)

(

⎟

⎠

⎞

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

CIC

where:

fin is the data input rate to the channel under consideration.

SCIC, the scale factor, is a programmable unsigned integer

between 0 and 20.

The attenuation of the data into the CIC stage should be

controlled in 6 dB increments. For the best dynamic range, SCIC

should be set to the smallest value possible (lowest attenuation

possible) without creating an overflow condition. This can be

accomplished safely using the following equation, where

input_level is the largest possible fraction of the full-scale value

at the input port. This value is output from the NCO stage and

pipelined into the CIC filter.

(

)

(

) 5

log

level

input

CIC

ceil

CIC

(

)

level

input

CIC

Bypass

The fifth-order CIC filter can be bypassed when no decimation

is required of it. When it is bypassed, the scaling operation is

not performed. In bypass mode, the output of the CIC filter is

the same as the input of the CIC filter.

CIC Rejection

Table 13 illustrates the amount of bandwidth as a percentage of

the data rate into the CIC stage, which can be protected with

various decimation rates and alias rejection specifications. The

maximum input rate into the CIC is 150 MHz (the same as the

maximum input port data rate). The data may be scaled to any

other allowable sample rate.

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