AD6636PCB datasheet(68/72 Pages) AD

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AD6636

Rev. 0 | Page 68 of 72

<12>: Port B, AGC 4 Enable Bit. Similar to Bit <13> for AGC 4.

<11>: Port B, AGC 3 Enable Bit. Similar to Bit <13> for AGC 3.

<10>: Port B, AGC 2 Enable Bit. Similar to Bit <13> for AGC 2.

<9>: Port B, AGC 1 Enable Bit. Similar to Bit <13> for r AGC 1.

<8>: Port B, AGC 0 Enable Bit. Similar to Bit <13> for AGC 0.

<7>: Port A Append RSSI Bit. When this bit is set, an RSSI word

is appended to every I/Q output sample, irrespective of whether

or not the RSSI word is updated in the AGC. When this bit is

cleared, an RSSI word is appended to an I/Q output sample only

when the RSSI word is updated. The RSSI word is not output for

subsequent I/Q samples until the next time RSSI is updated

again in the AGC.

<6>: Port A, Data Format Bit. When this bit is set, the port is

configured for 8-bit parallel I/Q mode. When this bit is cleared,

the port is configured for 16-bit interleaved I/Q mode. See the

Parallel Port Output section.

<5>: Port A, AGC 5 Enable Bit. When this bit is set, AGC 5 data

(I/Q data) is output on parallel output Port A (data bus). When

this bit is cleared, AGC 5 data does not appear on output Port C.

<4>: Port A, AGC 4 Enable Bit. Similar to Bit <5> for AGC 4.

<3>: Port A, AGC 3 Enable Bit. Similar to Bit <5> for AGC 3.

<2>: Port A, AGC 2 Enable Bit. Similar to Bit <5> for AGC 2.

<1>: Port A, AGC 1 Enable Bit. Similar to Bit <5> for AGC 1.

<0>: Port A, AGC 0 Enable Bit. Similar to Bit <5> for AGC 0.

Output Port Control <9:0>

<9:8>: PCLK Divisor Bits. When a parallel port is in master

mode, the PCLK is derived from the PLL_CLK. These bits

define the value of the divisor used to divide the PLL_CLK to

obtain the PCLK. These bits are don’t care in slave mode.

Table 43. PCLK Divisor Bits

PCLK Divisor <7:6>

Divisor Value

<7>: PCLK Master Mode Bit. When the PCLK master mode bit

is set, the PCLK pin is configured as an output and the PCLK is

driven by the PLL_CLK. Data is transferred out of the AD6636

synchronous to this output clock. When this bit is cleared, the

PCLK pin is configured as an input. The user is required to

provide a PCLK, and data is transferred out of the AD6636

synchronous to this input clock. On power-up, this bit is cleared

to avoid contention on the PCLK pin.

<6:4>: Complex Control Bits. These bits are described in

Table 44.

Table 44. Complex Control Bits

Complex Control <6:4>

Comment

000

No complex filters

Stream control register controls

AGC usage.

001

Str0/1 combined

Ch 0 and Ch 1 form a complex

filter.

010

Str0/1 combined,

Str2/3 combined

Ch 0 and Ch 1 form a complex

filter; Ch 2 and Ch 3 form a

complex filter.

011

Str0/1 combined,

Str2/3 combined,

Str 4/5 combined

Ch 0 and Ch 1 form a complex

filter; Ch 2 and Ch 3 form a

complex filter; Ch 4 and Ch 5

form a complex filter.

101

Str0/1 combined

Ch 0 and Ch 1 form a biphase

filter.

110

Str0/1 combined,

Str2/3 combined

Ch 0 and Ch 1 form a biphase

filter; Ch 2 and Ch 3 to form a

biphase filter.

111

Str0/1 combined,

Str2/3 combined,

Str 4/5 combined

Ch 0 and Ch 1 to form a biphase

filter; Ch 2 and Ch 3 to form a

biphase filter; Ch 4 and Ch 5 to

form a biphase filter.

<3:0>: Stream Control Bits. These bits are described in Table 45.

Table 45. Stream Control Bits

Stream

Control Bits

Output Streams (str0, str1,

str2, str3, str4, str5)

Number of

Streams

0000

Ch 0/1 combined; Ch 2, Ch 3,

Ch 4, Ch 5 independent

0001

Ch 0/1/2 combined; Ch 3, Ch 4,

Ch 5 independent

0010

Ch 0/1/2/3 combined; Ch 4, Ch

5 independent

0011

Ch 0/1/2/3/4 combined; Ch 5

independent

0100

Ch 0/1/2/3/4/5 combined

0101

Ch 0/1/2 combined, Ch 3/4/5

combined

0110

Ch 0/1 combined, Ch 2/3

combined, Ch 4/5 combined

0111

Ch 0/1 combined, Ch 2/3

combined, Ch 4, Ch 5

independent

1000

Ch 0/1/2 combined, Ch 3/4

combined, 5 independent

1001

Ch 0/1/2/3 combined, Ch 4/5

combined.

Default

Independent channels

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