AD6636PCB datasheet(33/72 Pages) AD

33 / 72 page

AD6636

Rev. 0 | Page 33 of 72

Because this filter is nondecimating, the input and output rates

are both same and equal to one of the following:

fMRCF = fHB2, if HB2 is bypassed

fMRCF =

HB2

, if HB2 is not bypassed

If fPLLCLK is the PLL clock and if

PLLCLK

TAPS

MRCF

≥

then half of the PLL clock can be used for processing (power

savings). Otherwise, the PLL clock should be used.

Bypass

The MRCF filter can be used in normal operation or bypassed

using the MRCF bypass bit in the MRCF control register. When

the filter is bypassed, the output of the filter is the same as the

input of the filter. Bypassing the MRCF filter when not required

results in power savings.

Scaling

The output of the MRCF filter can be scaled by using the 2-bit

MRCF scaling word in the MRCF control register. Table 18

shows the valid values for the 2-bit word and their correspond-

ing settings.

Table 18. MRCF Scaling Factor Settings

MRCF Scale Word [1:0]

Scaling Factor

18.06 dB attenuation

12.04 dB attenuation

6.02 dB attenuation

No scaling, 0 dB

DECIMATING RAM COEFFICIENT FILTER (DRCF)

Following the MRCF is the programmable DRCF FIR filter.

This filter can calculate up to 64 asymmetrical filter taps or up

to 128 symmetrical filter taps. The filter is also capable of a

programmable decimation rate of from 1 to 16. A flexible

coefficient offset feature allows loading multiple filters into the

coefficient RAM and changing the filters on the fly. The

decimation phase feature allows a polyphase implementation,

where multiple AD6636 channels are used for processing a

single carrier.

The DRCF filter has 20-bit input and output data and 14-bit

coefficient data. The number of filter taps to calculate is

programmable and is set in the DRCF taps register. The value

of the number of taps minus one is written to this register.

For example, a value of 19 in the register corresponds to

20 filter taps.

The decimation rate is programmable using the 4-bit DRCF

decimation rate word in the DRCF control register. Again, the

value written is the decimation rate minus one.

Bypass

The DRCF filter can be used in normal operation or bypassed

using the DRCF bypass bit in the DRCF control register. When

the DRCF filter is bypassed, no scaling is applied and the output

of the filter is the same as the input to the DRCF filter.

Scaling

The output of the DRCF filter can be scaled using the 2-bit

DRCF scaling word in the DRCF control register. Table 19 lists

the valid values for the 2-bit word and their corresponding

settings.

Table 19. DRCF Scaling Factor Settings

DRCF Scale Word [1:0]

Scaling Factor

18.06 dB attenuation

12.04 dB attenuation

6.02 dB attenuation

No scaling, 0 dB

Symmetry

The DRCF filter does not require symmetrical filters. However,

if the filter is symmetrical, then the symmetry bit in the DRCF

control register should be set. When this bit is set, only half of

the impulse response needs to be programmed into the DRCF

coefficient memory registers. For example, if the number of

filter taps is equal to 15 or 16 and the filter is symmetrical, then

only eight coefficients need to be written into the coefficient

memory. Because a total of 64 taps can be written into the

memory registers, the DRCF can perform 64 asymmetrical filter

taps or 128 symmetrical filter taps.

Coefficient Offset

More than one set of filter coefficients can be loaded into

coefficient RAM at any given time (given sufficient RAM

space). The coefficient offset can be used in this case to access

the two or more different filters. By changing the coefficient

offset, the filter coefficients being accessed can be changed on

the fly. This decimal offset value is programmed in the DRCF

coefficient offset register. When this value is changed during the

calculation of a particular output data sample, the sample

calculation is completed using the old coefficients, and the new

coefficient offset from the next data sample calculation is used.

Decimation Phase

When more than one channel of AD6636 is used to process one

carrier, polyphase implementation of corresponding channels’

DRCF or CRCF is possible using the decimation phase feature.

This feature can be used only under certain conditions. The

decimation phase is programmed using the 4-bit DRCF

decimation phase word of the DRCF control register.

AD6636PCB датащи(PDF) 33 Page - Analog Devices

AD6636PCB датащи(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL