AD6636PCB datasheet(62/72 Pages) AD

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AD6636

Rev. 0 | Page 62 of 72

<0>: Gain Control Enable Bit. This bit controls the configura-

tion of the EXP<2:0> bits for Channel A. When the gain control

enable bit is Logic 1, the EXP<2:0> bits are configured as

outputs. When this bit is cleared, the EXP<2:0> bits are inputs.

Port A Dwell Timer <19:0>

This register is used to set the dwell time for the gain control

block. When gain control block is active and detects a decrease

in the signal level below the lower threshold value (program-

mable), a dwell time counter is initiated to provide temporal

hysteresis. Doing so prevents the gain from being switched

continuously. Note that the dwell timer is turned on only after a

drop below the lower threshold is detected in the signal level.

Port A Power Monitor Period <23:0>

This register is used in the power monitoring logic to set the

period of time for which ADC input data is monitored. This

value represents the monitor period in number of ADC port

clock cycles.

Port A Power Monitor Output <23:0>

This register is read-only and contains the current status of the

power monitoring logic output. The output is dependent on the

power monitoring mode selected. When the power monitor

block is enabled, this register is updated at the end of each

power monitor period. This register is updated even if an

interrupt signal is not generated.

Port A Upper Threshold <9:0>

This register serves the dual purpose of specifying the upper

threshold value in the gain control block and in the power

monitoring block, depending on which block is active. Any

ADC port input data having a magnitude greater than this value

triggers a gain change in the gain control block. Any ADC port

input data having a magnitude greater than this value is

monitored in the power monitoring block (in peak detect or

threshold crossing mode). The value of the register is compared

with the absolute magnitude of the input port data. For real

input, the absolute magnitude is the same as the input data; for

positive and negative data, the absolute magnitude is the value

of the data after removing the negative sign.

Port A Lower Threshold <9:0>

This register is used in the gain control block and represents the

magnitude of the lower threshold for ADC port input data. Any

ADC input data having a magnitude below the lower threshold

initiates the dwell time counter. The value of the register is

compared with the absolute magnitude of the input port data.

For real input, the absolute magnitude is the same as the input

data; for positive and negative data, the absolute magnitude is

the value of the data after removing the negative sign.

Port A Signal Monitor <4:0>

This register controls the functions of the power monitoring

block.

<4>: Disable Power Monitor Period Timer Bit. When this bit is

set, the power monitor period timer no longer controls the

update of the power monitor holding register. A user read to the

power monitor holding register updates this register. When this

bit is cleared, the power monitor period register controls the

timer and, therefore, controls the update rate of the power

monitor holding register.

<3>: Clear-on-Read Bit. When this bit is set, the power monitor

holding register is cleared every time this register is read. This

bit controls whether the power monitoring function is cleared

after a read of the power monitor period register. If this bit is

set, the monitoring function is cleared after the read. If this bit is

Logic 0, the monitoring function is not cleared. This bit is a

don’t care if the disable integration counter bit is clear.

<2:1>: Monitor Function Select Bits. Table 33 lists the functions

of these bits.

Table 33. Monitor Function Select Bits

Monitor Function Select

Function Enabled

Peak Detect Mode

Mean Power Monitor Mode

Threshold Crossing Mode

Invalid Selection

<0>: Monitor Enable Bit. When this bit is set, the power

monitoring function is enabled and operates as selected by

Bits <2:1> of the signal monitor register. When this bit is

cleared, the power monitoring function is disabled and the

signal monitor register <2:1> bits are don’t care. This bit defaults

to 0 on power-up.

Note: Gain control, dwell timer, power monitor period, signal

monitor, power monitoring output, lower threshold and upper

threshold registers for Ports B, C, and D work similarly to the

corresponding registers definitions for Port A.

CHANNEL REGISTER MAP

Channel control registers are common to all six channels, and

access to specific channels is determined by the channel I/O

access register (Address 0x02).

NCO Control <15:0>

These bits control the NCO operation.

<8:7>: NCO Sync Start Select Bits. These bits determine which

SYNC input pin is used by this channel for a start synchroniza-

tion operation. Table 34 describes the selection.

Table 34. Sync Start Select Bits

NCO Control <8:7>

SYNC Pin Used for Start Synchronization

SYNC0

SYNC1

SYNC2

SYNC3

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