AD6636PCB datasheet(53/72 Pages) AD

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AD6636

Rev. 0 | Page 53 of 72

The chip select (CS) is an active-low input that signals when an

access is active on its programming port pins. When the

read/write cycle is complete, the AD6636 drives DTACK low.

The DTACK signal goes high again after either the CS or DS

signal is driven high. Because the DTACK pin is an open-drain

output with a weak internal pull-up resistor (70 kΩ), an external

pull-up resistor is recommended (see Figure 50). Figure 15 and

Figure 16 are the timing diagrams for read and write cycles

using the microport in MNM mode.

For an asynchronous write operation on the Motorola mode

microport, the CPUCLK should be running. Set up the data and

address buses. Pull the R/W and DS signals low and then pull

the CS signal low. The DTACK goes low after a few clock cycles

to indicate that the write access is complete and that CS can be

pulled high to disable the microport. For an asynchronous read

operation on the Motorola mode microport, set up the address

bus and three-state the data bus. Pull the RD signal low and

then pull the CS signal low. The DTACK goes low after a few

clock cycles to indicate that valid data is on the data bus.

Accessing Multiple AD6636 Devices

If multiple AD6636 devices are on a single board, the microport

pins for these devices can be shared. In this configuration, a

single programming device (DSP, FPGA, or microcontroller)

can program all AD6636 devices connected to it.

Each AD6636 has four CHIPID pins that can be connected in

16 different ways. During a write/read access, the internal

circuitry checks to see if the CHIPID bits in the chip I/O access

control register (Address 0x02) are the same as the logic levels

of the CHIPID pins (hardwired to the part). If the CHIPID bits

and the CHIPID pins have the same value, then a write/read

access is completed; otherwise, the access is ignored.

To program multiple devices using the same microport control

and data buses, the devices should have separate CHIPID pin

configurations. A write/read access can be made only on the

intended chip; all other chips would ignore the access.

JTAG BOUNDARY SCAN

The AD6636 supports a subset of the IEEE Standard 1149.1

specification. For details of the standard, see the IEEE Standard

Test Access Port and Boundary-Scan Architecture, an IEEE-1149

publication.

The AD6636 has five pins associated with the JTAG interface.

These pins, listed in Table 27, are used to access the on-chip test

access port. All input JTAG pins are pull-up except for TCLK,

which is pull-down.

Table 27. Boundary Scan Test Pins

Name

Description

TRST

Test Access Port Reset

TCLK

Test Clock

TMS

Test Access Port Mode Select

TDI

Test Data Input

TDO

Test Data Output

The AD6636 supports three op codes, listed in Table 28. These

instructions set the mode of the JTAG interface.

Table 28. Boundary Scan Op Codes

Instruction

Op Code

BYPASS

SAMPLE/PRELOAD

EXTEST

A BSDL file for this device is available. Contact Analog Devices

Inc. for more information.

EXTEST (2'b00)

Places the IC into an external boundary-test mode and selects

the boundary-scan register to be connected between TDI and

TDO. During this operation, the boundary-scan register is

accessed to drive-test data off-chip via boundary outputs and

receive test data off-chip from boundary inputs.

SAMPLE/PRELOAD (2'b01)

Allows the IC to remain in normal functional mode and selects

the boundary-scan register to be connected between TDI and

TDO. The boundary-scan register can be accessed by a scan

operation to take a sample of the functional data entering and

leaving the IC. Also, test data can be preloaded into the

boundary scan register before an EXTEST instruction.

BYPASS (2'b11)

Allows the IC to remain in normal functional mode and selects

a 1-bit bypass register between TDI and TDO. During this

instruction, serial data is transferred from TDI to TDO without

affecting operation of the IC.

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