AD6636PCB datasheet(44/72 Pages) AD

44 / 72 page

AD6636

Rev. 0 | Page 44 of 72

When an output data sample is available for output from an

AGC, the parallel port initiates the transfer by pulling the

PxREQ signal high. In response, the processor receiving the

data needs to pull the PxACK signal high, acknowledging that it

is ready to receive the signal. In Figure 40, PxACK is already

pulled high and, therefore, the 16-bit I data is output on the data

bus on the next PCLK rising edge after PxREQ is driven logic

high. The PxIQ signal also goes high to indicate that I data is

available on the data bus. The next PCLK cycle brings the

Q data onto the data bus. In this cycle, the PxIQ signal is driven

low. When I data and Q data are output, the channel indicator

pins PxCH[2:0] indicate the data source (AGC number).

Figure 40 is the timing diagram for interleaved I/Q mode with

the AGC gain word disabled. Figure 41 is a similar timing

diagram with the AGC gain word. I and Q data are as explained

for Figure 40. In the PCLK cycle after the Q data, the AGC gain

word is output on the data bus and the PxGAIN signal is pulled

high to indicate that the gain word is available on the parallel

port. Therefore, a minimum of three or four PCLK cycles are

required to output one sample of output data on the parallel

port without or with the AGC gain word, respectively.

Parallel IQ Mode

In this mode, eight bits of I data and eight bits of Q data are

output on the data bus simultaneously during one PCLK cycle.

The I byte is the most significant byte of the port, while the Q

byte is the least significant byte. The PAIQ and PBIQ output

indicator pins are set high during the PCLK cycle. Note that if

data from multiple AGCs are output consecutively, the PAIQ

and PBIQ output indicator pins remain high until data from all

channels is output.

The PACH[2:0] and PBCH[2:0] pins provide a 3-bit binary

value indicating the source (AGC number) of the data currently

being output. Figure 42 is the timing diagram for parallel I/Q

mode.

PCLKn

tDPREQ

PxREQ

PxACK

tDPP

Px [15:0]

I[15:0]

Q[15:0]

PxIQ

tDPIQ

PxCH [2:0]

PxCH [2:0] = CHANNEL #

tDPCH

GAIN [11:0] +

0000

PxGAIN

tDPGAIN

Figure 41. Interleaved I/Q Mode with an AGC Gain Word

AD6636PCB датащи(PDF) 44 Page - Analog Devices

AD6636PCB датащи(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL