HT45F5R datasheet(20/138 Pages) HOLTEK

20 / 138 page

Rev. 1.10

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Rev. 1.10

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HT45F5R

Charger ASSP Flash MCU

HT45F5R

Charger ASSP Flash MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Thedevicetakesadvantageoftheusualfeaturesfoundwithin

RISCmicrocontrollersprovidingincreasedspeedofoperationandPeriodicperformance.The

pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution

areoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranch

orcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,which

carriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,

etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.

CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectly

addressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitectural

featuresensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/Oand

A/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-

cost,high-volumeproductionforcontrollerapplications

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHIRCorLIRCoscillatorissubdividedintofour

internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe

beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4

clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms

oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive

instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare

effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe

contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe

instructionwilltakeonemoreinstructioncycletoexecute.

Fet�h Inst. (PC+�)

Exe�ute Inst. (PC+1)

Os�illato� Clo�k

(Syste� Clo�k)

Phase Clo�k T1

Phase Clo�k T�

Phase Clo�k T4

P�og�a� Counte�

Pipelining

PC+1

PC+�

Fet�h Inst. (PC+1)

Exe�ute Inst. (PC)

Exe�ute Inst. (PC-1)

Fet�h Inst. (PC)

System Clock and Pipelining

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