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HT45F5R датащи(PDF) 41 Page - Holtek Semiconductor Inc |
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HT45F5R датащи(HTML) 41 Page - Holtek Semiconductor Inc |
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41 / 138 page ![]() Rev. 1.10 40 De�e��e� 1�� �01� Rev. 1.10 41 De�e��e� 1�� �01� HT45F5R Charger ASSP Flash MCU HT45F5R Charger ASSP Flash MCU IDLE2 Mode TheIDLE2ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitinthe SCCregisterishighandtheFSIDENbitintheSCCregisterislow.IntheIDLE2Modethesystem oscillatorwillbeinhibitedfromdrivingtheCPUbutifthesystemoscillatorishighspeedsystem oscillator,itmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperational. Control Register Theregisters,SCCandHIRCC,areusedtocontrolthesystemclockandthecorresponding oscillatorconfigurations. Register Name Bit 7 6 5 4 3 2 1 0 SCC CKS� CKS1 CKS0 — — — FHIDEN FSIDEN HIRCC — — — — — — HIRCF HIRCEN System Operating Mode Control Registers List SCC Register Bit 7 6 5 4 3 2 1 0 Na�e CKS� CKS1 CKS0 — — — FHIDEN FSIDEN R/W R/W R/W R/W — — — R/W R/W POR 0 0 0 — — — 0 0 Bit7~5 CKS2~CKS0:Systemclockselection 000:fH 001:fH/2 010:fH/4 011:fH/8 100:fH/16 101:fH/32 110:fH/64 111:fSUB Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In additiontothesystemclocksourcedirectlyderivedfromfHorfSUB,adividedversion ofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource. Bit4~2 Unimplemented,readas"0" Bit1 FHIDEN:HighFrequencyoscillatorcontrolwhenCPUisswitchedoff 0:Disable 1:Enable Thisbitisusedtocontrolwhetherthehighspeedoscillatorisactivatedorstopped whentheCPUisswitchedoffbyexecutingan"HALT"instruction. Bit0 FSIDEN:LowFrequencyoscillatorcontrolwhenCPUisswitchedoff 0:Disable 1:Enable Thisbitisusedtocontrolwhetherthelowspeedoscillatorisactivatedorstopped whentheCPUisswitchedoffbyexecutingan"HALT"instruction.TheLIRC oscillatoriscontrolledbythisbittogetherwiththeWDTfunctionenablecontrol whentheWDTfunctionisenabled.Ifthisbitisclearedto0buttheWDTfunctionis enabled,theLIRCoscillatorwillalsobeenabled. |
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