HT32F22366 datasheet(16/56 Pages) HOLTEK

16 / 56 page

Rev. 1.00

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CPU. The data and address lines are multiplexed in order to reduce the number of pins required to

connect to the external devices. The read/write timing of the bus can be adjusted to meet the timing

specification of the external devices. Note the interface only supports asynchronous 8-bit or 16-bit

bus interface.

Universal Serial Bus Device Controller – USB

▆

Complies with USB 2.0 full-speed (12 Mbps) specification

▆

On-chip USB full-speed transceiver

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1 control endpoint (EP0) for control transfer

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3 single-buffered endpoints for bulk and interrupt transfer

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4 double-buffered endpoints for bulk, interrupt and isochronous transfer

▆

1024 bytes EP-SRAM used as the endpoint data buffers

The USB device controller is compliant with the USB 2.0 full-speed specification. There is one

control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024 bytes SRAM

is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding

registers, which provides maximum flexibility for various applications. The integrated USB full-

speed transceiver helps to minimize the overall system complexity and cost. The USB functional

block also contains the resume and suspend feature to meet the requirements of low-power

consumption.

Advanced Encryption Standard – AES

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Supports AES Encrypt / Decrypt Function

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Supports AES ECB/CBC/CTR mode

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Supports Key Size 128, 192 and 256 bits

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Supports 4 words Initial Vector for CBC and CTR mode

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8 × 32 bits ( Each IN and OUT FIFO Capacity ) for 2 AES Data blocks

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Supports DMA Interface

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Supports Word Data Swap Function

The AES core supports encryption and decryption function. AES only supports 128 bits input data

to do encryption or decryption. Hardware does not pad any bits of input data. Software need to do

pad action at first.

Secure Digital Input Output – SDIO

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Supports two different data bus modes: 1-bit (default) and 4-bit

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Supports two different speed modes: Normal speed (default) and High speed

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SD clock frequency of up to 48 MHz

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SPI mode and MMC stream mode not supported

The SDIO includes a command register, argument register, response registers, data buffer, timeout

counter and error detection logic. The SDIO supports single block and multi-block data transfers

and is compatible with the PDMA, minimizing processor intervention for large data transfers.

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