Rev. 1.00

5 of 56

�ove��e� 0�� �01�

HT3�F1�365/HT3�F1�366/HT3�F��366

List of Figures

Figu�e 1. Block Diag�a� ......................................................................................................................... 19

Figu�e �. Me�o�y Map............................................................................................................................ �0

Figu�e 3. Clock St�uctu�e ........................................................................................................................ �3

Figu�e 4. 46-pin QF� Pin Assign�ent ................................................................................................... �4

Figu�e 5. 48-pin LQFP Pin Assign�ent................................................................................................... �5

Figu�e 6. 64-pin LQFP Assign�ent......................................................................................................... �6

Figu�e �. 100-pin LQFP Assign�ent....................................................................................................... ��

Figu�e 8. ADC Sa�pling �etwo�k Model ................................................................................................ 4�

Figu�e 9. I�C Ti�ing Diag�a�s................................................................................................................ 44

Figu�e 10. SPI Ti�ing Diag�a�s – SPI Maste� Mode ............................................................................. 45

Figu�e 11. SPI Ti�ing Diag�a�s – SPI Slave Mode with CPHA=1......................................................... 46

Figu�e 1�. Ti�ing of I�S Maste� Mode .................................................................................................... 4�

Figu�e 13. Ti�ing of I�S Slave Mode ...................................................................................................... 4�

Figu�e 14. SDIO Default Mode ............................................................................................................... 48

Figu�e 15. SDIO High-speed Mode ........................................................................................................ 49

Figu�e 16. USB Signal Rise Ti�e and Fall Ti�e and C�oss-Point Voltage (VCRS) Definition .................. 50