HT32F22366 datasheet(15/56 Pages) HOLTEK

15 / 56 page

Rev. 1.00

15 of 56

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3�-Bit A��® Co�tex®-M3 MCU

HT3�F1�365/HT3�F1�366/HT3�F��366

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Supports byte, half-word & word data size

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Programmable CRC initial seed value

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CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit

data

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Supports PDMA to complete a CRC computation of a block of memory

The CRC calculation unit is an error detection technique test algorithm which is used to verify data

transmission or storage data correctness. A CRC calculation takes a data stream or a block of data

as input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed by

a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored

data stream is calculated by the same generator polynomial as described above. If the new CRC

code result does not match the one calculated earlier, that means data stream contains a data error.

Peripheral Direct Memory Access – PDMA

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12 channels with trigger source grouping

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8/16/32-bit width data transfer

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Supports Address increment, decrement or fixed mode

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4-level programmable channel priority

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Auto reload mode

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Supports trigger source:

ADC, SPI, EBI, CRC, USART, UART, I2C, I2S, GPTM, MCTM, SCI, AES, SDIO and software

request

The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals

and the system memory on the AHB bus. Each PDMA channel has a source address, destination

address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid

interrupt service routine execution. It improves system performance as the software does not need

to join each data movement operation.

External Bus Interface – EBI

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Programmable interface for various memory types

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Translate the AHB transactions into the appropriate external device protocol

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Memory bank regions and independent chip select control for each memory bank

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Programmable timings to support a wide range of devices

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Includes page read mode

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Automatic translation when the AHB transaction width and external memory interface width is

different

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Write buffer to decrease the stalling of the AHB write burst transaction

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Multiplexed and non-multiplexed address and data line configurations

● Up to 25 address lines

● Up to 16-bit data bus width

The external bus interface is able to access external parallel interface devices such as SRAM,

Flash and LCD modules. The interface is memory mapped into the internal address map of the

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