HT32F22366 datasheet(12/56 Pages) HOLTEK

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Rev. 1.00

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Real Time Clock – RTC

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32-bit up-counter with a programmable prescaler

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Alarm function

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Interrupt and Wake-up event

The Real Time Clock, RTC for short, includes an APB interface, a 32-bit count-up counter, a

control register, a prescaler, a compare register and a status register. Most of the RTC circuits are

located in the Backup Domain except for the APB interface. The APB interface is located in the

VDD15 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from

the power control unit when the VDD15 power domain is powered off, that is when the device enters

the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume

signal from the Power-Down mode.

Inter-integrated Circuit – I2C

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Supports both master and slave modes with a frequency of up to 1 MHz

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Provide an arbitration function and clock synchronization

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Supports 7-bit and 10-bit addressing modes and general call addressing

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Supports slave multi-addressing mode with maskable address

The I2C Module is an internal circuit allowing communication with an external I2C interface which

is an industry standard two line serial interface used for connection to external hardware. These

two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module

provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode

and (3) 1 MHz in the Fast mode plus mode. The SCL period generation register is used to setup

different kinds of duty cycle implementations for the SCL pulse.

The SDA line which is connected directly to the I2C bus is a bi-directional data line between the

master and slave devices and is used for data transmission and reception. The I2C module also has

an arbitration detect function and clock synchronization to prevent situations where more than one

master attempts to transmit data to the I2C bus at the same time.

Serial Peripheral Interface – SPI

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Supports both master and slave mode

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Frequency of up to (fPCLK/2) MHz for master mode and (fPCLK/3) MHz for slave mode

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FIFO Depth: 8 levels

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Multi-master and multi-slave operation

The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function

in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and

output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device

acts as a master device which controls the data flow using the SEL and SCK signals to indicate the

start of data communication and the data sampling rate. To receive a data byte, the streamed data

bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data

transmission is carried out in a similar way but in a reverse sequence. The mode fault detection

provides a capability for multi-master applications.

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