HT32F22366 datasheet(41/56 Pages) HOLTEK

41 / 56 page

Rev. 1.00

41 of 56

�ove��e� 0�� 01�

3�-Bit A��® Co�tex®-M3 MCU

HT3�F1�365/HT3�F1�366/HT3�F��366

ADC Characteristics

Table 19. ADC Characteristics

TA = �5 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

VDDA

Ope�ating voltage

—

�.5

3.3

3.6

VADCI�

A/D Conve�te� input voltage

�ange

—

VREF+

A/D Conve�te� Refe�ence

voltage

—

VDDA

IADC

Cu��ent consu�ption

VDDA = 3.3 V

—

0.85

�A

IADC_D�

Powe� down cu��ent

consu�ption

VDDA = 3.3 V

—

0.1

μA

fADC

A/D Conve�te� clock

—

0.�

—

MHz

Sa�pling �ate

—

0.05

—

MHz

TDL

Data latency

—

1�.5

—

1/fADC

Cycles

TS&H

Sa�pling & hold ti�e

—

3.5

—

1/fADC

Cycles

TADCCO�V A/D Conve�te� conve�sion

ti�e

—

1/fADC

Cycles

Input sa�pling switch

�esistance

—

kΩ

Input sa�pling capacitance

�o pin/pad capacitance

included

—

tSU

Sta�tup up ti�e

—

μs

�

Resolution

—

1�

—

�its

I�L

Integ�al �on-linea�ity e��o�

fS = �50 kHz� VDDA = 3.3 V

—

±�

±5

LSB

D�L

Diffe�ential �on-linea�ity

e��o�

fS = �50 kHz� VDDA = 3.3 V

—

±1

—

LSB

Offset e��o�

—

±10

LSB

Gain e��o�

—

±10

LSB

�ote: 1. Gua�anteed �y design� not tested in p�oduction.

2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input

stage whe�e CI is the sto�age capacito�� RI is the �esistance of the sa�pling switch and RS

is the output i�pedance of the signal sou�ce VS. �o��ally the sa�pling phase du�ation is

app�oxi�ately� 3.5/fADC. The capacitance� CI� �ust �e cha�ged within this ti�e f�a�e and

it �ust �e ensu�ed that the voltage at its te��inals �eco�es sufficiently close to VS fo�

accu�acy. To gua�antee this� RS �ay not have an a��it�a�ily la�ge value.

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