HT32F22366 datasheet(44/56 Pages) HOLTEK

44 / 56 page

Rev. 1.00

44 of 56

�ove��e� 0�� 01�

3�-Bit A��® Co�tex®-M3 MCU

HT3�F1�365/HT3�F1�366/HT3�F��366

Symbol

Parameter

Standard Mode Fast Mode Fast Mode Plus

Unit

Min.

Max.

Min. Max.

Min.

Max.

tSU(STA)

START condition setup

ti�e

500

—

1�5

—

tH(STA)

START condition hold ti�e

—

tSU(STO)

STOP condition setup ti�e

500

—

1�5

—

�ote: 1. Gua�anteed �y design� not tested in p�oduction.

�. To achieve 100 kHz standa�d �ode� the pe�iphe�al clock f�equency �ust �e highe� than � MHz.

3. To achieve 400 kHz fast �ode� the pe�iphe�al clock f�equency �ust �e highe� than 8 MHz.

4. To achieve 1 MHz fast �ode plus� the pe�iphe�al clock f�equency �ust �e highe� than �0 MHz.

5. The a�ove cha�acte�istic pa�a�ete�s of the I�C �us ti�ing a�e �ased on: SEQ_FILTER = 01

and COMB_FILTER_En is disa�led.

tSU(STA)

tH(STA)

tFALL

tSCL(L)

tRISE

tSCL(H)

tH(SDA)

tSU(SDA)

tSU(STO)

SCL

SDA

Figure 9. I2C Timing Diagrams

SPI Characteristics

Table 23. SPI Characteristics

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

SPI Master mode

fSCK

(1/tSCK)

SPI �aste� output SCK

clock f�equency

Maste� �odeSPI pe�iphe�al

clock f�equency fPCLK

—

fPCLK/�

MHz

tSCK(H)

tSCK(L)

SCK clock high and low

ti�e

—

tSCK/� - � — tSCK/� + 1 ns

tV(MO)

Data output valid ti�e

—

tH(MO)

Data output hold ti�e

—

�

—

tSU(MI)

Data input setup ti�e

—

tH(MI)

Data input hold ti�e

—

SPI Slave mode

fSCK

(1/tSCK)

SPI slave input SCK clock

f�equency

Slave �ode

SPI pe�iphe�al clock

f�equency fPCLK

—

fPCLK/3

MHz

DutySCK

SPI slave input SCK clock

duty cycle

—

�0

tSU(SEL)

SEL ena�le setup ti�e

—

3 × tPCLK

—

tH(SEL)

SEL ena�le hold ti�e

—

� × tPCLK

—

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