SLG46121V datasheet(34/98 Pages) DIALOG

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000-0046121--106

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SLG46121

8.2 Matrix Output Table

Table 16. Matrix Output Table

Address

Matrix Output Signal Function

Matrix Output

Number

reg <5:0>

Pin 3 digital out source

reg <11:6>

Pin 4 digital out source

reg <17:12>

Pin 5 digital out source

reg <23:18>

Pin 6 digital out source

reg <29:24>

Pin 6 output enable

reg <35:30>

in0 of LUT2_0 (Clock Input of DFF0)

reg <41:36>

in1 of LUT2_0 (Data Input of DFF0)

reg <47:42>

in0 of LUT2_1 (Clock Input of DFF1)

reg <53:48>

in1 of LUT2_1 (Data Input of DFF1)

reg <59:54>

in0 of LUT2_2 (Clock Input of DFF2)

reg <65:60>

in1 of LUT2_2 (Data Input of DFF2)

reg <71:66>

in0 of LUT2_3 (Clock Input of DFF3)

reg <77:72>

in1 of LUT2_3 (Data Input of DFF3)

reg <83:78>

in0 of LUT2_4

reg <89:84>

in1 of LUT2_4

reg <95:90>

in0 of Inverter INV_0

reg <101:96>

Pin 12 digital out source

reg <107:102>

in0 of LUT3_0 (Clock Input of DFF4 with nReset/nSet)

reg <113:108>

in1 of LUT3_0 (Data input of DFF4 with nReset/nSet)18

reg <119:114>

in2 of LUT3_0 (Resetb or Setb of DFF4 with nReset/nSet)

reg <125:120>

in0 of LUT3_1 (Clock Input of DFF5 with nReset/nSet)

reg <131:126>

in1 of LUT3_1 (Data input of DFF5 with nReset/nSet)21

reg <137:132>

in2 of LUT3_1 (Resetb or Setb of DFF5 with nReset/nSet)

reg <143:138>

in0 of LUT3_2 (Clock Input of DFF6 with nReset/nSet)

reg <149:144>

in1 of LUT3_2 (Data input of DFF6 with nReset/nSet)24

reg <155:150>

in2 of LUT3_2 (Resetb or Setb of DFF6 with nReset/nSet)

reg <161:156>

in0 of LUT3_3 (Clock Input of DFF7 with nReset/nSet)

reg <167:162>

in1 of LUT3_3 (Data input of DFF7 with nReset/nSet)27

reg <173:168>

in2 of LUT3_3 (Resetb or Setb of DFF7 with nReset/nSet)

reg <179:174>

in0 of LUT3_4

reg <185:180>

in1 of LUT3_4

reg <191:186>

in2 of LUT3_4

reg <197:192>

in0 of LUT3_5

reg <203:198>

in1 of LUT3_5

reg <209:204>

in2 of LUT3_5

reg <215:210>

in0 of LUT3_6

reg <221:216>

in1 of LUT3_6

reg <227:222>

in2 of LUT3_6

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