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SLG46121V датащи(PDF) 16 Page - Dialog Semiconductor |
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SLG46121V датащи(HTML) 16 Page - Dialog Semiconductor |
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16 / 98 page ![]() 000-0046121--106 Page 15 of 97 SLG46121 5.10 Typical Counter/Delay Offset Measurements 5.11 Expected Delays and Widths Table 3. Typical Counter/Delay Offset Measurements. Parameter RC OSC Freq RC OSC Power VDD = 1.8V VDD = 3.3V VDD = 5.0V Unit offset 25 kHz auto 19 14 12 s offset 2 MHz auto 7 4 4 s frequency settling time 25 kHz auto 19 14 12 s frequency settling time 2 MHz auto 14 14 14 s variable (CLK period) 25 kHz forced 0-40 0-40 0-40 s variable (CLK period) 2 MHz forced 0-0.5 0-0.5 0-0.5 s tpd (non-delayed edge) 25 kHz/ 2 MHz either 35 14 10 ns Table 4. Expected Delays and Widths for Programmable Delay (typical). Symbol Parameter Note VDD/VDD2= 1.8V VDD/VDD2= 3.3V VDD/VDD2 = 5.0V Unit time1 Width, 1 cell PDLY mode:(any)edge detect, edge detect output 256.7 120.8 110 ns time1 Width, 2 cell PDLY mode:(any)edge detect, edge detect output 564.4 262.7 225 ns time1 Width, 3 cell PDLY mode:(any)edge detect, edge detect output 873.5 405 340 ns time1 Width, 4 cell PDLY mode:(any)edge detect, edge detect output 11.82.3 547.5 450 ns time2 Delay, 1 cell PDLY mode:(any)edge detect, edge detect output 48.2 20 14 ns time2 Delay, 2 cell PDLY mode:(any)edge detect, edge detect output 48.2 20.1 14 ns time2 Delay, 3 cell PDLY mode:(any)edge detect, edge detect output 48.2 20.1 14 ns time2 Delay, 4 cell PDLY mode:(any)edge detect, edge detect output 48.3 20.1 14 ns time1 Delay, 1 cell PDLY mode: both edge delay (shared macrocell inputs) 357.9 162.2 110 ns time1 Delay, 2 cell PDLY mode: both edge delay (shared macrocell inputs) 666.1 304.3 220 ns time1 Delay, 3 cell PDLY mode: both edge delay (shared macrocell inputs) 974.7 446.3 335 ns time1 Delay, 4 cell PDLY mode: both edge delay (shared macrocell inputs) 1283.8 588.8 450 ns time1 Width CNT3/DLY3 Rising Edge Detect (shared macrocell inputs) 136.6 73.4 140 ns time1 Width CNT3/DLY3 Falling Edge Detect (shared macrocell inputs) 130.6 71 140 ns time1 Width CNT3/DLY3 Both Edge Detect (shared macrocell inputs) 133.05 72 140 ns |
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