SLG46121V datasheet(85/98 Pages) DIALOG

85 / 98 page

000-0046121--106

Page 84 of 97

SLG46121

reg<501>

Counter/delay2 mode selection

0: Delay Mode

1: Counter Mode

reg<504:502>

Counter/delay2 Clock Source select

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter1 Overflow

reg<512:505>

Counter/delay2 Control Data

1 - 256 (delay time = (counter control data +2) /freq )

reg <514:513>

Delay2 Mode Select or asynchronous counter reset

00: on both falling and rising edges(for delay & count-

er reset)

01: on falling edge only (for delay & counter reset)

10: on rising edge only (for delay & counter reset)

11: no delay on either falling or rising edges / high

level reset for counter mode

reg<517>

LUT4_0 or Counter2 select

0: LUT4_0

1: Counter2

LUT4_1 or Counter/Delay3

reg<533:518>

LUT4_1 data or the following

reg<518>

Counter/delay3 mode selection

0: Delay Mode 1: Counter Mode

reg<521:519>

Counter/delay3 Clock Source select

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter1 Overflow

reg<529:522>

Counter/delay3 Control Data

1 - 256 (delay time = (counter control data +2) /freq )

reg<531:530>

Delay3 Mode Select or asynchronous counter reset

00: on both falling and rising edges(for delay & count-

er reset)

01: on falling edge only (for delay & counter reset)

10: on rising edge only (for delay & counter reset)

11: no delay on either falling or rising edges

reg<534>

LUT4_1 or Counter3 select

0: LUT4_1

1: Counter3

RC Osc

reg<535>

Force RC oscillator on

0: Auto Power on

1: Force Power on

reg<536>

RC Oscillator frequency control

0: 25 kHz

1: 2 MHz

reg<538:537>

Osc clock pre-divider

00:div1

01:div2

10: div4

11: div8

Address

Signal Function

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