SLG46121V datasheet(82/98 Pages) DIALOG

82 / 98 page

000-0046121--106

Page 81 of 97

SLG46121

reg<251:246>

Matrix Out: In0 of LUT3_8 or Input of Pipe delay

reg<257:252>

Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay

reg<263:258>

Matrix Out: In2 of LUT3_8 or Clock of Pipe delay

reg<269:264>

Matrix Out: In0 of LUT4_0 or Input for delay2(couter2)

external clock

reg<275:270>

Matrix Out: In1 of LUT4_0 or Input for delay2 da-

ta(counter2 reset)

reg<281:276>

Matrix Out: In2 of LUT4_0

reg<287:282>

Matrix Out: In3 of LUT4_0

reg<293:288>

Matrix Out: In0 of LUT4_1 or Input for delay3(couter3)

external clock

reg<299:294>

Matrix Out: In1 of LUT4_1 or Input for delay3 da-

ta(counter3 reset)

reg<305:300>

Matrix Out: In2 of LUT4_1

reg<311:306>

Matrix Out: In3 of LUT4_1

reg<317:312>

Matrix Out: Input for delay0 data(counter0 external

clock)

reg<323:318>

Matrix Out: Input for delay1(counter1) external clock

reg<329:324>

Matrix Out: Input for delay1 data(counter1 reset)

reg<335:330>

Matrix Out: Not used

reg<341:336>

Matrix Out: pdb(power down) for ACMP0

reg<347:342>

Matrix Out: pdb(power down) for ACMP1

reg<353:348>

Matrix Out: Input for programmable delay (deglitch filter

input)

reg<359:354>

Matrix Out: Power down for osc (1: Power down)

reg<365:360>

Matrix Out: PIN8 Digital Output Source

reg<371:366>

Matrix Out: PIN9 Digital Output Source

reg<377:372>

Matrix Out: PIN10 Digital Output Source

reg<383:378>

Matrix Out: Output Enable of PIN10

reg<389:384>

Reserved

reg<395:390>

Reserved

LUT2_0 or DFF0

reg<399:396>

LUT2_0 data or the following

reg<396>

DFF0 or Latch select

0: DFF function

1: Latch function

reg<397>

DFF0 output select

0: Q output

1: nQ output

reg<398>

DFF0 initial polarity select

0: Low

1: High

LUT2_1 or DFF1

reg<403:400>

LUT2_1 data or the following

0: DFF function

1: Latch function

reg<400>

DFF1 or Latch select

0: DFF function

1: Latch function

reg<401>

DFF1 output select

0: Q output

1: nQ output

Address

Signal Function

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