SLG46121V datasheet(55/98 Pages) DIALOG

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000-0046121--106

Page 54 of 97

SLG46121

10.4.2 4-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 8-Bit Counter / Delay Register Settings

Table 45. CNT/DLY2 Register Settings

Signal Function

Address

Counter/delay2

Mode Selection

reg <501>

0: Delay Mode

1: Counter Mode

Counter/delay2

Clock Source Select

reg <504:502>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter1 Overflow

Counter/delay2

Control Data

reg <512:505>

1 – 256 (delay time = (counter control data +2) /freq)

Delay2 Mode Select

or asynchronous

counter reset

reg <514:513>

00: Delay on both falling and rising edges (for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset Delay)

10: on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

LUT4_0 or Count-

er2 select

reg <517>

0: LUT4_0

1: Counter2

Table 46. CNT/DLY3 Register Settings

Signal Function

Address

Counter/delay3

Mode Selection

reg <518>

0: Delay Mode

1: Counter Mode

Counter/delay3

Clock Source Select

reg <521:519>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter2 Overflow

Counter/delay3

Control Data

reg <529:522>

1 – 256 (delay time = (counter control data +2) /freq)

Delay3 Mode Select

or asynchronous

counter reset

reg <531:530>

00: Delay on both falling and rising edges (for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset Delay)

10: on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

LUT4_1 or Count-

er3 select

reg <534>

0: LUT4_1

1: Counter3

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