SLG46121V datasheet(91/98 Pages) DIALOG

91 / 98 page

000-0046121--106

Page 90 of 97

SLG46121

reg<689>

PIN12 driver strength selection

0: 1X

1: 2X

reg<690>

Pipe delay OUT1 polarity select bit

0: Non-inverted

1: Inverted

reg<698:691>

8-bit pattern id

reg<699>

filter0 output polarity select

0: Non-inverting

1: Inverting

reg<701:700>

Reserved

reg<702>

GPIO quick charge enable

0: Disable

1: Enable

reg<706:703>

Reserved

reg<707>

Force bandgap on

0: Auto-mode

1: Enable

reg<708>

VREF1 Output Active Buffer Control

0: Disabled

1: Enabled

reg<711:709>

VREF1 Output Source Select

000: ACMP0 reference voltage

001: ACMP1 reference voltage

100: VDD/2

101: VDD/3

110: VDD/4

reg<712>

NVM data read disable

0: Disable (read enable)

1: Enable (read disable)

reg<713>

NVM power down (or NVM data programming disable) 0: None (or programming enable)

1: Power Down (or programming disable)

reg<714>

Power Divider Power

0: Power down

1: Power On

reg<715>

POR Auto Power detect

0: Enable

1: Disable

reg<716>

Charge pump for analog macrocell enable (when VDD

<=2.7V turn on)

0: Disable (automatic on/off control)

1: Enable (always on)

reg<717>

VDD bypass enable

0: Regulator auto on

1: Regualtor off (VDD bypass)

reg<718>

PIN2 edge detect mode

0: rising edge

1: falling edge

reg<719>

Bypass the pin2

0: PIN2 edge active

1: PIN2 high active

reg<720>

PIN2 reset enable

0: Disable

1: Enable

reg<721>

Reserved

reg<727:722>

Reserved

reg<735:728>

Reserved

reg<741:736>

Reserved

reg<743:742>

Delay value select for programmable delay & edge de-

tector (VDD = 3.3V, typical condition)

00: 163 ns

01: 305 ns

10: 446 ns

11: 588 ns

reg<745:744>

Select the edge mode of programmable delay & edge

detector

00: rising edge detector

01: falling edge detector

10: both edge detector

11: both edge delay

Address

Signal Function

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