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SLG46121V датащи(PDF) 18 Page - Dialog Semiconductor

номер детали SLG46121V
подробное описание детали  Personal Computers and Servers
PDF  98 Pages
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производитель  DIALOG [Dialog Semiconductor]
домашняя страница  http://www.dialog-semiconductor.com/
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SLG46121V датащи(HTML) 18 Page - Dialog Semiconductor

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Page 17 of 97
SLG46121
6.0 Summary of Macrocell Function
6.1 I/O Pins
•
Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
•
Open Drain NMOS and Open Drain PMOS Outputs
•
Push Pull Outputs
•
Analog I/O
•
10 k
/100 k/1 Mpull-up/pull-down resistors
6.2 Connection Matrix
•
Digital matrix for circuit connections based on user design
6.3 Analog Comparators (2 total)
•
Selectable hysteresis 0 mV/25 mV/50 mV/200 mV and selectable gain 1x/0.5x/0.33x/0.25x
6.4 Voltage Reference
•
Used for references on Analog Comparators
•
Can also be driven to external pins
6.5 Combinational Logic Look Up Tables (LUTs – 5 total)
•
One 2-bit Lookup Tables
•
Four 3-bit Lookup Tables
6.6 Combination Function Macrocells (12 total)
•
Four Selectable DFF/Latches or 2-bit LUTs
•
Four Selectable DFF/Latches or 3-bit LUTs
•
One Selectable Pipe Delay or 3-bit LUT
•
Two Selectable CNT/DLYs or 4-bit LUTs
•
One Programmable Delay or Deglitch Filter
6.7 Delays/Counters (2 total)
•
One 8-bit delay/counter with external clock/reset: Range 1-255 clock cycles
•
One 14-bit delay/counter with external clock: Range 1-16383 clock cycles
6.8 Pipe Delay (Part of Combination Function Macrocell)
•
8 stage / 2 output
•
Two 1-8 stage selectable outputs
•
One 1 stage fixed output
6.9 Additional Logic Functions (Part of Combination Function Macrocell)
•
One Deglitch filter macrocell
•
One Programmable Delay
• 163 ns / 305 ns / 446 ns / 588 ns @ 3.3 V
• Includes Edge Detection function



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