AD9925BBCZ datasheet(62/96 Pages) AD

62 / 96 page

AD9925

Rev. A | Page 62 of 96

R REGISTER BANK 1

egister

D updated, except where noted. L

= SCK

Table 37. AFE Register Map

ddress

Data Bit Content

Default Value

COMPLETE LISTING FO

All r

s are V

ight gray cells

updated, and dark gray cells = SG line updated.

[11:0]

OPRMODE

AFE Operation Modes (See Table 45 for detail)

[9:0]

VGAGAIN

VGA Gain

[7:0]

CLAMPLEVEL

ptical Black Clamp Leve

[11:0]

CTLMODE

AFE Control Modes (See Table 46 for detail)

Table 38. Miscellaneous Regist

it Content

lt Value

er Map

Defau

Addres

Data B

ption

[17:0]

3FF8

STBY1POL

Polarities for Output Signals during Standby 1 Mode.

[17:0]

3FF8

STBY2POL

Polarities for Output Signals during Standby 2 Mode.

[17:0]

STBY3POL

ode.

larities for Output Signals during Standby 3 M

[17:0]

3FF8

OCONTPOL

Polarities for Output Signals When OUTCONTROL = 0.

[0]

SW_RST

Software Reset. 1: Reset all registers to default, then self clear back

to 0.

[0]

OUTCONTROL

inactive.

utput Control. 0: Make all outputs dc

[0]

SYNCENABLE

Configures Pin 52 as a SYNC Input (= 1) or CLPOB/PBLK Output (= 0).

[0]

SYNCPOL

SYNC Active Polarity (0: Active Low).

[0]

SYNCSUSPEND

Suspend Clocks during SYNC Active (1: Suspend).

[0]

TGCORE_RSTB

Timing Core Reset Bar. 0: Reset TG Core, 1: Resume Operation.

[0]

OSC_PWRDOW

wered Down).

O Oscillator Power-Down (0: Oscillator Is Po

UNUSED

Set to 0.

[0]

TEST

Internal Use Only. Must be set to 0.

[11:0]

VD updated registers.

UPDATE

rial Update. Line (HD) in the field to update

[0]

PREVENTUP-

DATE

events the update of the VD updated registers. 1: Prevent Update.

[23:0]

MODE

MODE Register.

UNUSED

Set to 0.

[0]

OUTPUTPBLK

Assigns Output for Pin 52 When Configured as Output.

0: CLPOB, 1: PBLK.

[0]

DVCMODE

1: Enable DVC Mode. VD counter will reset every 2 fields, instead of

every field. VDLEN register should be programmed to the total num-

ber of lines contained in 2 fields, e.g., VDLEN = 525 lines will results

in 262.5 lines in each field.

[0]

INVERT_DCLK

1: Invert the DCLK Output.

[2:0]

[3]

[5:4]

[6]

[7]

[8]

SHUT_EXTRA

Set to 0.

Selects FG_TRIG Signal to VSUB Pin (See Page 43).

Set to 0.

H3HBLKOFF, Set to 1 to Enable H3/H4 Outputs during HBLK (See

Page 19).

Set to 0.

Combines FG_TRIG and VSUB Signals (See Page 43).

[3:0]

FG_TRIGEN

FG_TRIG Signal Enable (See Page 43).

[0]

FG_TRIGPOL

FG_TRIG Start Polarity.

[11:0]

FG_TRIGLIN1

FG_TRIG First Toggle Position, Line Location.

[12:0]

FG_TRIGPIX1

FG_TRIG First Toggle Position, Pixel Location.

[11:0]

FG_TRIGLIN2

FG_TRIG Second Toggle Position, Line Location.

[12:0]

FG_TRIGPIX2

FG_TRIG Second Toggle Position, Pixel Location.

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