AD9925BBCZ datasheet(6/96 Pages) AD

6 / 96 page

AD9925

Rev. A | Page 6 of 96

ANALOG SPECIFICATIONS

AVDD1 = 3.0 V, fCLI = 36 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CDS

Input Characteristics Definition.1

Allowable CCD Reset Transient

500

Maximum Input Range before Saturation

0 dB CDS Gain (Default Setting)

1.0

V p-p

−2 dB CDS Gain

1.25

V p-p

−4 dB CDS Gain

1.6

V p-p

Maximum CCD Black Pixel Amplitude

+200/–100

Positive Offset Definition1

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution

1024

Steps

Gain Monotonicity

Guaranteed

Gain Range

Minimum Gain (VGA Code 0)

Maximum Gain (VGA Code 1023)

BLACK LEVEL CLAMP

Clamp Level Resolution

256

Steps

Clamp Level

Measured at ADC Output.

Minimum Clamp Level (Code 0)

LSB

Maximum Clamp Level (Code 255)

255

LSB

ANALOG-TO-DIGITAL CONVERTER (ADC)

Resolution

Bits

Differential Nonlinearity (DNL)

–1.0

±0.5

+1.0

LSB

No Missing Codes

Guaranteed

Full-Scale Input Voltage

2.0

VOLTAGE REFERENCE

Reference Top Voltage (REFT)

2.0

Reference Bottom Voltage (REFB)

1.0

SYSTEM PERFORMANCE

Includes Entire Signal Chain.

Gain Accuracy

Low Gain (VGA Code 0)

5.0

5.5

6.0

Gain = (0.0351 × Code) + 5.5 dB.

Maximum Gain (VGA Code 1023)

40.5

41.5

42.5

Peak Nonlinearity, 500 mV Input Signal

0.1

12 dB Gain Applied.

Total Output Noise

0.8

LSB rms

AC Grounded Input, 6 dB Gain Ap-

plied.

Power Supply Rejection (PSR)

Measured with Step Change on

Supply.

1 Input signal characteristics are defined as

+200mV MAX

OPTICAL BLACK PIXEL

500mV TYP

RESET TRANSIENT

1V MAX

INPUT SIGNAL RANGE

(0dB CDS GAIN)

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