AD9925BBCZ datasheet(61/96 Pages) AD

61 / 96 page

AD9925

Rev. A | Page 61 of 96

iffe

nding

he particular reg

. Table 36 summ

four differe

pes of register u

tes:

SCK U

ted

: Some of the registers in Bank 1

as soo

h data bit

) is written. T

ters, sh

gray in the B

egister list, a

functi

o not requi

ng with the n

bounda

as power-up

eset functions. T

select r

Addr 0x7F i

k 1 and Bank

SCK u

VD U

ost of the r

ank 1,

field r

s in Bank 2, ar

dated at the nex

edge. B

dating these val

at the next VD

current field will not be corrupted, and the new register

values will be applied to the next field. Bank 1 register up-

VD falling edge by

VD up

o any HD line

e field. Note th

field registers are not affected by the UPDATE register.

SG Line Updated

: A few of the registers in Bank 1 are up-

f the SG active line, at the HD falling

he SUBCK signal, so that the

te until after the SG line has

ers are crosshatched in the

d Bank 3, all of the vertical

equence registers (Addr 0x00

ing Addr 0×7F) are updated at

ill be used. For example, in

cted Region 1 to use Vertical

outputs. This means that a write

done to the same register, the last one done before SCP1

will be the one that is updated. Likewise, register writes to

any Vertical Sequence 5 registers will be updated at SCP2,

o any Vertical Sequence 8 registers will

le 36. R

r Update Loca

Update Type

Description

Updating New Register Values

The AD99 5’s internal register are updated at d

rent times,

depe

on t

nt ty

pda

ister

pda

arizes the

are update

n as the 24t

(D23

hese regis-

aded in

ons that d

ank 1 r

re gati

re used for

ext VD

ry, such

egister (

and r

n Ban

he bank

2) is also

pdated

: M

egisters in B

as well as the

egister

y up

e up

ues

t VD falling

edge, the

dates may be further delayed past the

using the UPDATE registe (Addr 0x19). Th will delay

dates t

in th

at the Bank

dated at the end o

edge. These registers control t

SUBCK output will not upda

been completed. These regist

Bank 1 register list.

SCP Updated

: In Bank 2 an

pattern group and vertical s

through Addr 0xCF, exclud

the next SCP, where they w

Figure 77, this field has sele

Sequence 3 for the vertical

to any of the Vertical Sequence 3 registers, or any of the ver-

tical pattern group registers that are referenced by Vertical

Sequence 3, will be updated at SCP1. If multiple writes are

and register writes t

be updated at SCP3.

Tab

egiste

tio

SCK Update

Bank 1 Only

when the 24th data bit (D23) is clocked in.

VD Update

Bank 1, Bank

by using the UP

Addr 0x19 in Ba

UPDATE reg

ng edge. VD updated registers in Bank 1 may be delayed further

DATE register at

ister.

nk 1. Bank 2 updates will not be affected by th

SG Line Up

Bank 1 Only

HD falli

ine.

dated

pdated at the

ng edge at the end of the SG active l

SCP Update

Bank 2, Bank

e next SC

sed.

pdated at th

P when the register will be u

REGION 0

SCP 1

REGION 1

SCP 2

N 3

SCP 3

REGION 2

REGIO

XSG

SGLINE

SCP 0

SERIAL

WRITE

SCK

UPDATED

SCP 0

UPDAT

UPD

UPDATED

ATED

XV1 TO XV6

USE VSEQ2

USE VSEQ3

USE VSEQ5

USE VSEQ8

Figure 77. R

tions (

egister Update Loca

See Table 40 for Definitions)

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