AD9925BBCZ datasheet(59/96 Pages) AD

59 / 96 page

AD9925

Rev. A | Page 59 of 96

he 8-bit address and 24-bit data-

-bit op

s required, as

own in Figure 7

y regis

ewer than 24

wide, all 24 bi

ten for

egister. For exa

, if the registe

wide, t

upper 14 bits

on’t Cares an

lled with 0s during the serial write operation. If fewer than 24

dated with new data.

Figure 75 shows a more efficient way to write to the registers,

using the AD9925’s address automatic increment capability.

written first,

followed by multiple 24-bit data-words. Each new 24-bit data-

ally be written to the next highest register

ch 8-bit address,

us write operations

th any register location and may be used

ny as the entire

SERIAL INTERFACE TIMING

All of the internal registers of the AD9925 are accessed through

a 3-wire serial interface. Each register consists of an 8-bit address

Using this method, the lowest desired address is

and a 24-bit data-word. Both t

word are written starting with t e LSB. To write

each register,

a 32

eration i

4. Although

man

ters are f

bits

ts must be

writ

each r

mple

r is only 10

bits

hen the

are D

d may be

bits are written, the register will not be up

word will automatic

address. By eliminating the need to write ea

gister loading is achieved. Continuo

faster re

may be used starting wi

to write to as few as two registers or to as ma

SDATA

D21

D22

D23

SCK

tLS

tDS

8-BIT ADDRESS

24-BIT DATA

tLH

tDH

NOTES

1. SDATA BITS

LATCHED ON SCK

2. ALL 32 BITS

T BE WRITTEN: 8 BI

4. NEW DATA V

ES ARE UPDATED IN

IST

PARTICULAR

GISTER WRITTEN TO

3. IF THE REGISTER LENGTH IS < 24 BIT

BIT

74. Serial Wr

ARE

MUS

RISING EDGES. SCK M

TS FOR ADDRESS AND

IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS.

4 BITS FOR DATA.

ALU

THE SPECIFIED REG

S, THEN DON’T CARE

ER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE

S MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.

. SEE THE REGISTER

DATES SECTION FOR MORE INFORMATION.

Figure

ite Operati

SDATA

D22

D23

SCK

NOTES

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).

MULTIPLE SEQUE

L REGISTERS MAY B

UOU

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN,

SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN L

NTIA

E LOADED CONTIN

SLY.

FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.

OADED.

D22

D23

DATA FOR S

EGISTER A

DATA FOR NEXT

2345

TARTING

DDRESS

erial Write O

Figure 75. Continuous S

peration

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