AD9925BBCZ datasheet(60/96 Pages) AD

60 / 96 page

AD9925

Rev. A | Page 60 of 96

2, and BANK 3

dif

anks, r

ed to as Register

nk 1, Register B

ster Ba

. Figure 76 illust

s how the three

ed. Re

ank 1 and Ba

re backward

with the AD

gisters. Regi

Bank 1 contain

the

iscellaneous

ctions, VD/HD

ters,

ming core, CLPOB masking, VSG patterns, and shutter func-

information for the

eld i

ster Ba

contains new reg

r accessing

functi

ty. These additio

outputs allow th

5 to

support ne

Ds that requir

-phases of verti

writ

the AD9925, A

0x7F is used to

which addr

k is being writ

. To write to

data value

ritten. To wri

Bank 2, a data

ten. To

o Bank 3, a da

alue of 2 is writ

Note that Register Bank 1 contains many unused addresses.

s between Addr 0x00 and Addr 0x7F are

these addresses

ed addresses above 0x7F must not be

may not operate properly. The excep-

registers 0xE7, 0xEB, and 0xF2 through

0xF6, which may be written as specified on Page 43.

Default values for Register Bank 2 and Bank 3 are undefined after

ate values should be written into these regis-

plications where the

Bank 3 registers should

known values to prevent unpredict-

ver circuit.

The AD99 5 address space is d vided into three

ferent regis-

ter b

eferr

ank 2, and

Regi

nk 3

rate

banks are

divid

gister B

9995 re

nk 2 a

ster

compatib

s the regi

ters for

AFE, m

fun

parame

tions. Register Bank 2 contains all of the

vertical pattern groups, vertical sequences, and fi

nformation.

Regi

nk 3

isters fo

the XV7 and

XV8

onali

wer CC

nal

e 8

e AD992

cal clocking.

When

ing to

ess ban

of 0 is w

ddr

ten to

te to

specify

Bank 1, a

value of 1 is

writ

write t

ta v

ten.

Undefined addresse

considered Don’t Cares, and it is acceptable if

are filled in with all 0s during a continuous

tion. However, the undefin

written to, or the AD9925

tions are the FG_TRIG

power-up. Appropri

ter banks to ensure proper operation. In ap

XV7 and XV8 signals are not used, the

still be programmed with

able behavior in the V-dri

AFE REGISTERS

SWITCH TO

ADDR 0x00

ADDR

MISCELLANEOUS REGISTERS

VD/HD REGISTERS

TIMING CORE REGISTERS

CLPOB MASK REGISTERS

VSG PATTERN REGISTERS

SHUTTER REGISTERS

ADDR

ADDR 0x20

ADDR 0x30

ADDR 0x40

ADDR 0x50

ADDR 0x60

0x7F

0x10

VPAT0 TO VPAT9 REGISTERS

XV1 TO X

SWI

REGISTE

ADDR 0x00

VSEQ0 TO VSEQ9 REGISTERS

XV1 TO X

LD 0 TO FI

ADDR 0x7F

ADDR 0x80

ADD

ADDR 0x7E

ADD

ESS 0x7F

ADDR

ADDR 0x8F

FOR

V6 SIGNALS

TCH TO

ANK 1, BANK 3

FOR

V6 SIGNALS

R BANK 2

FIE

R 0xFF

ELD 5 REGISTERS

R 0xD0

R 0xCF

RITE TO ADDR

TO SWITCH REGISTER BANKS

0xFF

INVALID, DO NOT ACCESS

VPAT0 TO VPAT9 REGISTERS

FOR

XV7, XV8 SIGNALS

VSEQ0 TO VSEQ9 REGISTERS

FOR

XV7, XV8 SIGNALS

ADDR 0x77

ADDR 0x50

ADDR 0x4F

ADDR 0x7F

ADDR 0x00

ADDR 0xF

INVALID, DO NOT ACCESS

SWITCH TO

Figure 76.

Regi

Layout of Internal

ster Bank 1, Bank 2, and Bank 3

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