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AT83C5111 датащи(PDF) 61 Page - ATMEL Corporation |
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AT83C5111 датащи(HTML) 61 Page - ATMEL Corporation |
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61 / 86 page ![]() 61 AT8xC5111 4190A–8051–11/02 Table 1. Priority Bit Level Values A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 2. Address Vectors IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 011 102 1 1 3 (Highest) Interrupt Name Interrupt Address Vector Priority Number External Interrupt (INT0) 0003h 1 Timer0 (TF0) 000Bh 2 External Interrupt (INT1) 0013h 3 Timer1 (TF1) 001Bh 4 PCA (CF or CCFn) 0033h 5 UART (RI or TI) 0023h 6 SPI 004Bh 8 ADC 0043h 9 |
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