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AT83C5111 датащи(PDF) 38 Page - ATMEL Corporation |
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AT83C5111 датащи(HTML) 38 Page - ATMEL Corporation |
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38 / 86 page ![]() 38 AT8xC5111 4190A–8051–11/02 Figure 16 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 17). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. Figure 5. Data Transmission Format (CPHA = 1) Figure 15 shows the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 17). Figure 6. CPHA/SS Timing MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 MSB LSB 13 2 4 567 8 Capture Point SS (to Slave) MISO (from Slave) MOSI (from Master) SCK (CPOL = 1) SCK (CPOL = 0) SPEN (Internal) SCK Cycle Number Byte 1 Byte 2 Byte 3 MISO/MOSI Master SS Slave SS (CPHA = 1) Slave SS (CPHA = 0) |
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