AT83C5111 datasheet(42/86 Pages) ATMEL

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AT8xC5111

4190A–8051–11/02

Serial Peripheral Status Register

(SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions.

•

Data transfer complete

•

Write collision

•

Inconsistent logic level on SS pin (mode fault error)

Table 31 describes the SPSTA register and explains the use of every bit in the register:

Table 4. Serial Peripheral Status and Control Register

Reset value = 00X0XXXXb

7654

3210

SPIF

WCOL

MODF

----

Bit

Number

Bit

Mnemonic

R/W

Mode

Description

7SPIF

Serial Peripheral data transfer flag

Cleared by hardware to indicate data that transfer is in progress or has

been approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

6WCOL

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has

been approved by a clearing sequence.

Set by hardware to indicate that a collision has been detected.

Reserved

The value read from this bit is indeterminate. Do not set this bit

4MODF

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic

level, or has been approved by a clearing sequence.

Set by hardware to indicate that the SS pin is at inappropriate logic

level

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

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