AD7771BCPZ datasheet(16/99 Pages) AD

16 / 99 page

Data Sheet

AD7771

Rev. 0 | Page 15 of 98

Pin No.

Mnemonic

Type

Direction

Description

CONVST_SAR

Digital input

Input

Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table 13 for more

details. This pin also functions as the start for the SAR conversion in SPI control

mode.

ALERT/CS

Digital input

Input

Alert Output in Pin Control Mode (ALERT).

Chip Select in SPI Control Mode (CS).

DCLK2/SCLK

Digital input

Input

Data Clock Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15

for more details.

SPI Clock in SPI Control Mode (SCLK).

DCLK1/SDI

Digital input

Input

Data Clock Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 15

for more details.

SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the

device is configured in pin control mode with the SPI as the data output interface.

DCLK0/SDO

Digital output

Output

Data Clock Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 15

for more details.

SPI Data Output in SPI Control Mode (SDO).

DGND

Supply

Digital Ground.

DREGCAP

Supply

Output

Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a 1 µF

capacitor.

IOVDD

Supply

Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V.

IOVDD must not be lower than DREGCAP.

DOUT3

Digital output

I/O

Data Output Pin 3. If the device is configured in daisy-chain mode, this pin

acts as an input pin. See the Daisy-Chain Mode section for more details.

DOUT2

Digital output

I/O

Data Output Pin 2. If the device is configured in daisy-chain mode, this pin

acts as an input pin. See the Daisy-Chain Mode section for more details.

DOUT1

Digital output

Output

Data Output Pin 1.

DOUT0

Digital output

Output

Data Output Pin 0.

DCLK

Digital output

Output

Data Output Clock.

DRDY

Digital output

Output

Data Output Ready Pin.

XTAL1

Clock

Input

Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to

DGND. See Table 12 for more details.

XTAL2/MCLK

Clock

Input

Crystal 2 Input Connection (XTAL2). See Table 12 for more details.

CMOS Clock (MCLK). See Table 12 for more details.

START

Digital input

Input

Synchronization Pulse. This pin internally synchronizes an external START

asynchronous pulse with MCLK. The synchronize signal is shifted out by the

SYNC_OUT pin. If not in use, tie this pin to DGND. See the Phase Adjustment

section and the Digital Reset and Synchronization Pins section for more details.

SYNC_OUT

Digital output

Input

Synchronization Signal. This pin generates a synchronous pulse generated

and driven by hardware (via the START pin) or by software (GENERAL_USER_

CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin.

See the Phase Adjustment section and the Digital Reset and Synchronization

Pins section for more details.

SYNC_IN

Digital input

Input

Reset for the Internal Digital Block and Synchronize for Multiple Devices. See

the Digital Reset and Synchronization Pins section for more details.

RESET

Digital input

Input

Asynchronous Reset Pin. This pin resets all registers to their default value. It is

recommended to generate a pulse on this pin after the device is powered up

because a slow slew rate in the supplies may generate an incorrect initialization

in the digital block.

AIN7+

Analog input

Input

Analog Input Channel 7, Positive.

AIN7−

Analog input

Input

Analog Input Channel 7, Negative.

AIN6+

Analog input

Input

Analog Input Channel 6, Positive.

AIN6−

Analog input

Input

Analog Input Channel 6, Negative.

REF2+

Reference

Input

Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2− + 2.5V.

REF2−

Reference

Input

Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx.

Connect all the REFx− pins to the same potential.

AVDD1B

Supply

Positive Front-End Analog Supply for Channel 4 to Channel 7. Connect this pin

to AVDD1A.

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