AD7771BCPZ datasheet(39/99 Pages) AD

39 / 99 page

AD7771

Data Sheet

Rev. 0 | Page 38 of 98

There are two different ways to achieve a synchronous pulse if

the controller/processor cannot generate it as follows:

•

Applying an asynchronous pulse on the START pin, which

is then internally synchronized with the external MCLK

clock, and the resulting synchronous signal is output on

the SYNC_OUT pin.

•

Triggering the SYNC_OUT internally. When the AD7771

is configured in SPI control mode, toggling Bit 0 in the

GENERAL_USER_CONFIG_2 register generates a

synchronous pulse that is output on the SYNC_OUT pin.

The SYNC_IN and SYNC_OUT pins must be externally

connected if internal synchronization is used.

If multiple AD7771 devices must be synchronized, the

SYNC_OUT pin of one device can be connected to multiple

devices. This synchronization method requires the use of a

common MCLK signal for all the AD7771 devices connected,

as shown in Figure 110.

If the START pin is not used, tie it to DGND.

START

SYNC_IN

IOVDD

MCLK

SYNC_OUT

START

SYNC_IN

MCLK

SYNC_OUT

START

SYNC_IN

MCLK

SYNC_OUT

AD7771

SYNCHRONIZATION

LOGIC

ASYNCHRONOUS

PULSE

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MCLK

IOVDD

Figure 110. Multiple AD7771 Devices Synchronization

DIGITAL FILTERING

The AD7771 offers low latency sinc3 and sinc5 filters. Most

precision Σ-Δ ADCs use sinc filters because the sinc filters offer

a low latency path for applications requiring low bandwidth

signals, for example, in control loops or where application

specific postprocessing is required. The digital filter adds notches

at multiples of the sampling frequency.

The digital sinc3 filter implements three main notches, one at

the maximum ODR (128 kHz or 32 kHz, depending on the

power mode) and another two at the ODR frequency selected to

stop noise aliasing into the pass band. The sinc5 filter implements

five notches, one at the maximum ODR (128 kHz or 32 kHz,

depending on the power mode) and another four at the ODR

frequency selected to stop noise aliasing into the pass band.

It is recommended to select the sinc5 digital filter for output

data rates higher than 24 kSPS.

Figure 111 and Figure 112 show the typical filter transfer

function for the high resolution and low power modes using a

decimation rate of 32 samples for the sinc3 and sinc5 filters.

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

128

160

192

224

256

FREQUENCY (MHz)

SINC3

SINC5

Figure 111. Sinc3/Sinc5 Frequency Response in High Resoltuion Mode

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (MHz)

SINC3

SINC5

Figure 112. Sinc3/Sinc5 Frequency Response in Low Power Mode

The sample rate converter feature allows fine tuning of the

decimation rate, even for noninteger multiples of the decimation

rate. See the Sample Rate Converter (SRC) section for more

information on filter profiles for noninteger decimation rates.

SHUTDOWN MODE

The AD7771 can be placed in shutdown mode by pulling

AVDD2x to ground and connecting 1 MΩ resistance, pulled

low, to XTAL2/MCLK. In this mode, the average current

consumption is reduced to 1 mA, as shown in Figure 113.

AD7771BCPZ датащи(PDF) 39 Page - Analog Devices

AD7771BCPZ датащи(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

датащи скачать

ссылки URL