AD7771BCPZ datasheet(61/99 Pages) AD

61 / 99 page

AD7771

Data Sheet

Rev. 0 | Page 60 of 98

CH0_HEADER _+_CH0_8_BITS_MSB

CH0_16_BITS_LSB

SDO

Figure 137. SPI Readback, 16 Bits per Frame

SDO

CH0_HEADER _+_CH0_16_BITS_MSB

CH0_8_BITS_LSB_+_CH1_HEADER_+CH1_8_BITS_MSB

Figure 138. SPI Readback, 24 Bits per Frame

The SPI operates in multiples of 8 bits per frame; Figure 137 shows

a readback example in 16 bits per frames, and Figure 138 shows a

readback in 24 bits per frame.

Note that if the device is configured in SPI control mode, the

AD7771 generates a software reset if the SDI pin is sampled

high for 64 consecutive clocks. To avoid a reset or unwanted

which generates a readback command that is ignored by the

device, as explained in the SPI Software Reset section.

CALCULATING THE CRC CHECKSUM

The AD7771 implements two different CRC checksum

generators, one for the Σ-Δ results and another for the SPI

control mode.

The AD7771 uses a CRC polynomial to calculate the CRC

checksum value. The 8-bit CRC polynomial used is x8 + x2 + x + 1.

The polynomial is aligned so that its MSB is adjacent to the

leftmost Logic 1 of the data. An exclusive OR (XOR) function is

applied to the data to produce a new, shorter number. The

polynomial is again aligned so that its MSB is adjacent to the

leftmost Logic 1 of the new result, and the procedure is

repeated. This process is repeated until the original data is

reduced to a value less than the polynomial. This is the 8-bit

checksum.

An example of CRC calculation for 12-bit data is shown in

Table 42.

Table 42. Example CRC Calculation for 12-Bit Data1

Data

Polynomial

CRC

This table represents the division of the data; blank cells are for formatting

purposes.

Σ-Δ CRC Checksum

The CRC message is calculated internally by the AD7771 on

ADC pairs. The CRC is calculated using the ADC output data

from two ADCs and Bits[7:4] from the header. Therefore, 56 bits

are used to calculate the 8-bit CRC. This CRC is split between

the two channel headers. The CRC data covers channel pairings

as follows: Channel 0 and Channel 1, Channel 2 and Channel 3,

Channel 4 and Channel 5, and Channel 6 and Channel 7.

To generate the checksum, the data is left shifted by eight bits to

create a number ending in eight Logic 1s.

The CRC is calculated from 56 bits across two consecutive/

channel pairings (Channel 0 and Channel 1, Channel 2 and

Channel 3, Channel 4 and Channel 5, Channel 6, and Channel 7).

The 56 bits consist of the alert bit, the 3 bits for the first ADC

pairing channel, and the 24 bits of data of each pairing channel.

For example, for the second channel pairing, Channel 2 and

Channel 3,

56 bits = alert bit + 3 ADC channel bits (010) + 24 data bits

(Channel 2) + alert bit + 3 ADC channel bits (011) +

24 data bits (Channel 3)

SPI Control Mode Checksum

The CRC message is calculated internally by the AD7771. The

data transferred to the AD7771 uses the R/W bit, a 7-bit address,

and 8 bits of data for the CRC calculation.

The CRC calculated and appended to the data that is shifted

out uses a 0010 0000 header and 8 bits of data for the register

readback, as well as the 0010 header and 12 bits of SAR conversion

data for the SAR readback transfers.

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