AD7771BCPZ datasheet(43/99 Pages) AD

43 / 99 page

AD7771

Data Sheet

Rev. 0 | Page 42 of 98

SPI CONTROL

The second option for control and monitoring the AD7771 is

via the SPI. This option allows access to the full functionality

on the AD7771, including access to the SAR converter, phase

synchronization, offset and gain adjustment, diagnostics, and

the SRC. To use the SPI control, set the FORMAT0 and

FORMAT1 pins to logic high.

In this mode, the SPI can also read the Σ-Δ conversation data by

setting the SPI_SLAVE_MODE_EN bit.

The typical connection diagram for SPI control mode is shown

in Figure 115.

Functionality Available in SPI Control Mode

SPI control of the AD7771 offers the super set of the functions and

diagnostics. The SPI Control Functionality section describes the

functionality and diagnostics offered when in SPI control mode.

Offset and Gain Correction

Offset and gain registers are available for system calibration.

The gain register is preprogrammed during final production for

a PGA gain of 1, but can be overwritten with a new value if

required.

The gain register is 24 bits long and is split across three registers,

CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and

CHx_GAIN_LOWER_BYTE, which set the gain on a per

channel basis.

The gain value is relative to 0x555555, which represents a gain of 1.

The offset register is 24 bits long and is spread across three byte

registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_

BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is

0x000000 at power-up. Program the offset as a twos complement,

signed 24-bit number. If the channel gain is set to its nominal

value of 0x555555, an LSB of offset register adjustment changes

the digital output by −4/3 LSBs.

As an example of calibration, the offset measured is −200 LSB

(with both AINx± pins connected to the same potential).

An offset adjustment of −150 LSB changes the digital output by

−150 × (−4/3) = 200 LSBs (gain value = 0x555555), representing

this number as two complement, 0xFFFFFF − 0x96 + 1 =

0xFFFF70. Program the offset register as follows:

•

CHx_OFFSET_UPPER_BYTE = 0xFF

•

CHx_OFFSET_MID_BYTE = 0xFF

•

CHx_OFFSET_LOWER_BYTE = 0x70

Note that the offset compensation is performed before the gain

compensation. The gain is programmed during final testing for

PGAGAIN = 1. The gain register values can be overwritten; however,

after a reset or power cycle, the gain register values revert to the

hard coded programmed factory setting.

If the gain required is 0.75 of the nominal value (0x555555), the

value that must be programmed is

0x555555 × 0.75 = 0x400000

Then, an LSB of the offset register adjustment changes the digital

output by −4/3 × 0.75 = 1 LSB. Program the gain register as follows:

•

CHx_GAIN_UPPER_BYTE = 0x40

•

CHx_GAIN_MID_BYTE = 0x00

•

CHx_GAIN_LOWER_BYTE = 0x00

SPI Control Functionality

Global Control Functions

The following list details the global control functions of the

AD7771:

•

High resolution and low power modes of operation

•

ODR: SRC

•

Sinc3 and sinc5 filters

•

VCM buffer power-down

•

Internal/external reference selection

•

Enable, pre-Q, or bypassed reference buffer modes

•

Internal reference power-down

•

SAR diagnostic mux

•

SAR power-down

•

GPIO write/read

•

SPI SAR conversion readback

•

SPI slave mode—read Σ-Δ results

•

SDO and DOUTx drive strength

•

DOUTx mode

•

DCLK division

•

Internal LDO bypassed

•

Cyclic redundancy check (CRC) protection: enabled or

disabled

Per Channel Functions

The following list details the per channel functions of the

AD7771:

•

PGA gain.

•

Σ-Δ channel power-down.

•

Phase delay: synchronization phase offset per channel.

•

Calibration of offset.

•

Calibration of gain.

•

Σ-Δ input signal mux.

•

Channel error register.

•

PGA gain.

Phase Adjustment

The AD7771 phase delay can be adjusted to compensate for phase

mismatches between channels due to sensors or signal channel

phase errors connected to the AD7771. Achieve phase adjustment

by programming the CHx_SYNC_OFFSET register. This

programming delays the synchronization signal by a certain

number of modulator clocks (MOD_MCLK) to individually

initiate the digital filter for each Σ-Δ ADC.

The phase adjustment register is read during the pulse; conse-

quently, any further changes on the register have no effect unless a

pulse is generated (see the Digital Reset and Synchronization

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