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AD7771BCPZ датащи(PDF) 10 Page - Analog Devices

номер детали AD7771BCPZ
подробное описание детали  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  99 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7771BCPZ датащи(HTML) 10 Page - Analog Devices

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Data Sheet
AD7771
Rev. 0 | Page 9 of 98
DOUTx TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND (single-supply operation), AVDD2 −
AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V internal/external, MCLK = 8192 kHz; all
specifications at TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Description2
Test Conditions/Comments
Min
Typ
Max
Unit
t1
MCLK frequency
50:50
0.655
8.192
MHz
t2
MCLK low time
60
ns
t3
MCLK high time
60
ns
t4
DCLK high time
MCLK/2
121
ns
t5
DCLK low time
MCLK/2
121
ns
t6
MCLK falling edge to DCLK rising edge
45
ns
t7
MCLK falling edge to DCLK falling edge
45
ns
t8
DCLK rising edge to DRDY rising edge
2
ns
t9
DCLK rising edge to DRDY falling edge
1
ns
t10
DOUTx setup time
20
ns
t11
DOUTx hold time
20
ns
1
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
2
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
DCLK
DRDY
LSB
MSB
MSB – 1
LSB + 1
LSB
DOUTx
t2
t4
t5
t6
t7
t10
t11
t8
t9
t1
t3
Figure 2. Data Interface Timing Diagram



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