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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD7771BCPZ датащи(PDF) 8 Page - Analog Devices |
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AD7771BCPZ датащи(HTML) 8 Page - Analog Devices |
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8 / 99 page  Data Sheet AD7771 Rev. 0 | Page 7 of 98 Parameter Test Conditions/Comments Min Typ Max Unit Low Power PGAGAIN = 1 ±9 ±17 ppm of FSR Other PGA gains ±6 ±15 ppm of FSR Offset Error ±15 ±90 µV Offset Error Drift 0.25 µV/°C Over time −2 µV/1000 hours Offset Matching 25 µV Gain Error ±0.1 % FS Gain Error Drift vs. Temperature PGAGAIN = 1 ±0.75 ppm/°C Gain Matching ±0.1 % SAR ADC Speed and Performance Resolution 12 Bits Analog Input Range AVSS4 + 0.1 AVDD4 − 0.1 V Analog Input Common-Mode Range AVSS4 + 0.1 (AVDD4 + AVSS4)/2 AVDD4 − 0.1 V Analog Input Current ±100 nA Throughput 256 kSPS DC Accuracy Differential mode INL ±1.5 LSB Differential Nonlinearity (DNL) No missing codes (12-bit) −0.99 1 LSB Offset ±1 LSB Gain 12 LSB AC Performance Signal-to-Noise Ratio (SNR) 1 kHz 66 dB THD 1 kHz −81 dB VCM PIN Output (VCM) (AVDD1x + AVSSx)/2 V Load Current, IL 1 mA Load Regulation, ∆VOUT/∆IL 12 mV/mA Short-Circuit Current 5 mA LOGIC INPUTS Input Voltage High, VIH 0.7 × IOVDD V Low, VIL 0.4 V Hysteresis 0.1 V Input Currents −10 +10 µA LOGIC OUTPUTS3 Output Voltage High, VOH IOVDD ≥ 3 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.3 V ≤ IOVDD < 3 V, ISOURCE = 500 µA 0.8 × IOVDD V IOVDD < 2.3 V, ISOURCE = 200 µA 0.8 × IOVDD V Low, VOL IOVDD ≥ 3 V, ISINK = 2 mA 0.4 V 2.3 V ≤ IOVDD < 3 V, ISINK = 1 mA 0.4 V IOVDD < 2.3 V, ISINK = 100 µA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF Σ-Δ ADC Data Output Coding Twos complement SAR ADC Data Output Coding Binary |
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