WM8803CDTSLASHV datasheet(26/45 Pages) WOLFSON

номер детали	WM8803CDT/V

подробное описание детали	DIGITAL AUDIO INTERFACE RECEIVER

PDF	45 Pages

Scroll/Zoom	100%

производитель	WOLFSON [Wolfson Microelectronics plc]

домашняя страница	http://www.wolfsonmicro.com

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WM8803

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PP Rev 1.1 September 2003

WM8803

RXIN

UGPI

Figure 21 UGPI Output Usage Example (Data Input Switching Example)

CLOCK SWITCHING TRANSITION PERIOD SIGNAL OUTPUT

This section describes operation when UGPI is selected as the clock switching transition period

signal.

When there are changes to the PLL circuit locked/unlocked state, the clock switching transition

period signal reports to external circuits the output clock state switching transitions. This signal allows

the application to grasp the PLL lock state transitions and the timing of changes in the clock signals.

GPISEL is used to select this function.

After setting GPISEL, UGPI will initially output a high level. This is followed by output low level

pulses when the output clock changes due to changes in the PLL circuit locked/unlocked state.

In the lock pull-in process, the UGPI falling edge is triggered by the word clock generated by the XIN

clock after input data is detected and the PLL circuit locks, and by UGPI rising with the same timing

as ERROR after a fixed period has elapsed.

In the process where the PLL lock state is lost, the UGPI low level pulse is formed by UGPI falling

with the same timing as the PLL lock detection signal ERROR and by UGPI rising after a fixed

number of counts of the word clock generated from XIN.

WM8803CDT/V датащи(PDF) 26 Page - Wolfson Microelectronics plc