WM8803CDTSLASHV datasheet(21/45 Pages) WOLFSON

21 / 45 page

Product Preview

WM8803

PP Rev 1.1 September 2003

LEFT

CHANNEL

RIGHT

CHANNEL

LRCLK

BCLK

SDIN

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

16 to 24 bits

Figure 15 I

2S Data Input

LEFT

CHANNEL

RIGHT

CHANNEL

LRCLK

BCLK

SDIN

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

16,20,24 bits

Figure 16 MSB First Right-justified Data Input

OUTPUT DATA SWITCHING (SDIN, SDATO)

The SDATO pin outputs the demodulated data when the PLL circuit is locked and the SDIN input

data when the PLL circuit is unlocked. Switching between SDIN and SDATO is performed

automatically according to the locked/unlocked state of the PLL circuit. When XIN is the clock

source, input data synchronized with the CLKOUT, BCLK, and LRCLK clocks as the SDIN input data.

The SDIN input data can be output from SDATO by setting RDTSTA regardless of the PLL circuit

locked/unlocked state. In this case, the CLKOUT, BCLK, and LRCLK clocks will also be switched to

the XIN clock source. The switch occurs in synchronization with the LRCLK edge that follows the

setting of the RDTSTA.

The SDATO output data can be forcibly muted by setting RDTMUT. The muting processing is started

in synchronization with the LRCLK edge that follows the setting of the RDTMUT.

The SDATO output can be muted in the PLL locked state by setting RDTSEL.

These settings have the following priority order: RDTSEL < RDTSTA < RDTMUT.

WM8803CDT/V датащи(PDF) 21 Page - Wolfson Microelectronics plc

WM8803CDT/V датащи(HTML) 21 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

датащи скачать

ссылки URL