WM8803CDTSLASHV datasheet(15/45 Pages) WOLFSON

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WM8803

PP Rev 1.1 September 2003

PLLCK1

PLLCK0

XISEL1

XISEL0

CLKOUT

BCLK

LRCLK

22.5792MHz

5.6448MHz

88.2kHz

24.5760MHz

6.1440MHz

96kHz

33.8688MHz

8.4672MHz

132.3kHz

22.5792MHz

3.7632MHz

58.8kHz

24.5760MHz

4.0960MHz

64kHz

33.8688MHz

5.6448MHz

88.2kHz

22.5792MHz

5.6448MHz

88.2kHz

24.5760MHz

6.1440MHz

96kHz

33.8688MHz

8.4672MHz

132.3kHz

22.5792MHz

5.6448MHz

88.2kHz

24.5760MHz

6.1440MHz

96kHz

33.8688MHz

8.4672MHz

132.3kHz

Table 7 XIN Clock Source Mode Output Clocks

Note:

XISEL2 = 1, PLL unlocked state or forced setting

PLLCK1

PLLCK0

CLKOUT

BCLK

LRCLK

256 s

64fs

384fs

64fs

512fs

64fs

256fs

64fs

Table 8 PLL Clock Source Mode Output Clocks (PLL Locked State)

The CLKOUT output clock frequency can be set to 1/2 its normal value by MCKHFO, regardless of

the PLL locked/unlocked state. Clock switching using MCKHFO can also be performed in the PLL

locked state without losing that locked state, but clock continuity is not maintained.

If the audio output format is set to bi-phase data output, the BCLK output clock frequency will be

doubled to 128fs when the PLL circuit is locked. However, when unlocked, the BCLK frequencies

from Table 8 will be output. Note that the clock continuity is not maintained when this output format is

set.

CLOCK SYSTEM DIAGRAM

This section presents the relationship between the two master clock types and the switching and

clock dividing functions.

The items in square brackets near the switch and function blocks are the names of write commands.

The Lock/Unlock switch is switched automatically according to the locked/unlocked state of the PLL

circuit.

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