WM8803CDTSLASHV datasheet(16/45 Pages) WOLFSON

16 / 45 page

WM8803

Product Preview

PP Rev 1.1 September 2003

PLL

(256fs)

(384fs)

(512fs)

512/2fs)

Divider

1/2

Divider

1/2

1/3

1/4

1/6

1/8

Divider

1/256

1/384

1/512

[PLLOPR]

[PLLCK0]

[PLLCK1]

[AMPOPR]

[AMPCNT]

[XISEL0]

[XISEL1]

[XISEL2]

[XINSET]

Lock/Unlock

[OCKSEL]

[MCKHFO]

CLKOUT

BCLK

LRCLK

RXIN

XIN

XOUT

Figure 7 Master Clock System Diagram

NOTES ON CLOCK SOURCE SWITCHING

In states where the input fs calculation result is restricted by FLIMIT, if the WM8803 is switched by

OCKSEL from the PLL locked state (oscillator amplifier stopped) to the XIN source clock state, clock

continuity is maintained. However, ERROR will temporarily output a high level indicating an error.

This is because the oscillator amplifier will switch to the operating state at the same time as the

WM8803 switches to XIN source operation, and the input fs calculation will be restarted. The fs

calculated value prior to this time will be reset and when that is compared to the newly calculated fs

value, the transition will be handled as a change in fs.

With these settings, the oscillator amplifier must be set to continuous operation mode by AMPCNT

so that the clock source can be switched by OCKSEL while maintaining the ERROR state.

Note that when switching from the oscillator amplifier stopped state to XIN (the clock source while the

PLL circuit is locked), clocks which use XIN as the source will be output only after the oscillator

amplifier has started operating. Inversely, switching from XIN to the PLL circuit in the locked state

allows clocks to be output immediately. In both cases, clock continuity is maintained.

When neither an oscillator element nor an external clock is used, but the CLKOUT clock is supplied

to XIN. The VCO free-running frequency is output from CLKOUT; when the PLL is unlocked this

frequency will be in the range 10 to 16MHz. Clock signals created by dividing CLKOUT are output

from BCLK and LRCLK. However, these BCLK and LRCLK clocks will differ with the WM8803

sample rate set and will vary with the supply voltage and operating environment. Care is required

when using the CLKOUT, BCLK, and LRCLK clocks when the PLL circuit is unlocked.

WM8803CDT/V датащи(PDF) 16 Page - Wolfson Microelectronics plc

WM8803CDT/V датащи(HTML) 16 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

датащи скачать

ссылки URL