ACEX1 datasheet(19/86 Pages) ETC

19 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Cascade Chain

With the cascade chain, the ACEX 1K architecture can implement

functions that have a very wide fan-in. Adjacent LUTs can be used to

compute portions of the function in parallel; the cascade chain serially

connects the intermediate values. The cascade chain can use a logical AND

or logical OR (via De Morgan’s inversion) to connect the outputs of

adjacent LEs. With a delay as low as 0.6 ns per LE, each additional LE

provides four more inputs to the effective width of a function. Cascade

chain logic can be created automatically by the compiler during design

processing, or manually by the designer during design entry.

Cascade chains longer than eight bits are implemented automatically by

linking several LABs together. For easier routing, a long cascade chain

skips every other LAB in a row. A cascade chain longer than one LAB

skips either from even-numbered LAB to even-numbered LAB, or from

odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first

LAB in a row cascades to the first LE of the third LAB). The cascade chain

does not cross the center of the row (e.g., in the EP1K50 device, the cascade

chain stops at the eighteenth LAB, and a new one begins at the nineteenth

LAB). This break is due to the EAB’s placement in the middle of the row.

Figure 10 shows how the cascade function can connect adjacent LEs to

form functions with a wide fan-in. These examples show functions of 4n

variables implemented with n LEs. The LE delay is 1.3 ns; the cascade

chain delay is 0.6 ns. With the cascade chain, decoding a 16-bit address

requires 3.1 ns.

Figure 10. ACEX 1K Cascade Chain Operation

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

n – 1)..(4n – 4)]

d[3..0]

d[7..4]

LE1

LE2

LUT

AND Cascade Chain

OR Cascade Chain

d[(4

n – 1)..(4n – 4)]

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