ACEX1 datasheet(24/86 Pages) ETC

номер детали	ACEX1

подробное описание детали	Programmable Logic Device Family

PDF	86 Pages

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производитель	ETC [List of Unclassifed Manufacturers]

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24 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

In addition to the six clear and preset modes, ACEX 1K devices provide a

chip-wide reset pin that can reset all registers in the device. Use of this

feature is set during design entry. In any of the clear and preset modes, the

chip-wide reset overrides all other signals. Registers with asynchronous

presets may be preset when the chip-wide reset is asserted. Inversion can

be used to implement the asynchronous preset. Figure 12 shows examples

of how to setup the preset and clear inputs for the desired functionality.

Figure 12. ACEX 1K LE Clear & Preset Modes

Asynchronous Clear

Asynchronous Preset

Asynchronous Preset & Clear

Asynchronous Load without Clear or Preset

labctrl1

(Asynchronous

Load)

PRN

CLRN

NOT

labctrl1

(Asynchronous

Load)

Asynchronous Load with Clear

labctrl2

(Clear)

PRN

CLRN

NOT

(Asynchronous

Load)

Asynchronous Load with Preset

NOT

PRN

CLRN

labctrl1 or

labctrl2

PRN

CLRN

VCC

Chip-Wide Reset

PRN

CLRN

PRN

CLRN

VCC

Chip-WideReset

Chip-Wide Reset

data3

(Data)

labctrl1

labctrl2

(Preset)

data3

(Data)

data3

(Data)

labctrl1 or

labctrl2

labctrl1

labctrl2

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