ACEX1 datasheet(7/86 Pages) ETC

7 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input LUT, a

programmable flipflop, and dedicated signal paths for carry and cascade

functions. The eight LEs can be used to create medium-sized blocks of

logic—such as 8-bit counters, address decoders, or state machines—or

combined across LABs to create larger logic blocks. Each LAB represents

about 96 usable logic gates.

Signal interconnections within ACEX 1K devices (as well as to and from

device pins) are provided by the FastTrack Interconnect routing structure,

which is a series of fast, continuous row and column channels that run the

entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect routing structure. Each IOE

contains a bidirectional I/O buffer and a flipflop that can be used as either

an output or input register to feed input, output, or bidirectional signals.

When used with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 1.1 ns and

hold times of 0 ns. As outputs, these registers provide clock-to-output

times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1 shows a block diagram of the ACEX 1K device architecture. Each

group of LEs is combined into an LAB; groups of LABs are arranged into

rows and columns. Each row also contains a single EAB. The LABs and

EABs are interconnected by the FastTrack Interconnect routing structure.

IOEs are located at the end of each row and column of the FastTrack

Interconnect routing structure.

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