ACEX1 datasheet(22/86 Pages) ETC

22 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Normal Mode

The normal mode is suitable for general logic applications and wide

decoding functions that can take advantage of a cascade chain. In normal

mode, four data inputs from the LAB local interconnect and the carry-in

are inputs to a 4-input LUT. The compiler automatically selects the carry-

in or the DATA3 signal as one of the inputs to the LUT. The LUT output can

be combined with the cascade-in signal to form a cascade chain through

the cascade-out signal. Either the register or the LUT can be used to drive

both the local interconnect and the FastTrack Interconnect routing

structure at the same time.

The LUT and the register in the LE can be used independently (register

packing). To support register packing, the LE has two outputs; one drives

the local interconnect, and the other drives the FastTrack Interconnect

routing structure. The DATA4 signal can drive the register directly,

allowing the LUT to compute a function that is independent of the

registered signal; a 3-input function can be computed in the LUT, and a

fourth independent signal can be registered. Alternatively, a 4-input

function can be generated, and one of the inputs to this function can be

used to drive the register. The register in a packed LE can still use the clock

enable, clear, and preset signals in the LE. In a packed LE, the register can

drive the FastTrack Interconnect routing structure while the LUT drives

the local interconnect, or vice versa.

Arithmetic Mode

The arithmetic mode offers two 3-input LUTs that are ideal for

implementing adders, accumulators, and comparators. One LUT

computes a 3-input function; the other generates a carry output. As shown

in Figure 11, the first LUT uses the carry-in signal and two data inputs

from the LAB local interconnect to generate a combinatorial or registered

output. For example, in an adder, this output is the sum of three signals:

, b, and carry-in. The second LUT uses the same three signals to generate

a carry-out signal, thereby creating a carry chain. The arithmetic mode

also supports simultaneous use of the cascade chain.

Up/Down Counter Mode

The up/down counter mode offers counter enable, clock enable,

synchronous up/down control, and data loading options. These control

signals are generated by the data inputs from the LAB local interconnect,

the carry-in signal, and output feedback from the programmable register.

Two 3-input LUTs are used; one generates the counter data, and the other

generates the fast carry bit. A 2-to-1 multiplexer provides synchronous

loading. Data can also be loaded asynchronously with the clear and preset

ACEX1 датащи(PDF) 22 Page - List of Unclassifed Manufacturers

ACEX1 датащи(HTML) 22 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

датащи скачать

ссылки URL