ACEX1 datasheet(28/86 Pages) ETC

28 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

For improved routing, the row interconnect consists of a combination of

full-length and half-length channels. The full-length channels connect to

all LABs in a row; the half-length channels connect to the LABs in half of

the row. The EAB can be driven by the half-length channels in the left half

of the row and by the full-length channels. The EAB drives out to the full-

length channels. In addition to providing a predictable, row-wide

interconnect, this architecture provides increased routing resources. Two

neighboring LABs can be connected using a half-row channel, thereby

saving the other half of the channel for the other half of the row.

Table 6 summarizes the FastTrack Interconnect routing structure

resources available in each ACEX 1K device.

In addition to general-purpose I/O pins, ACEX 1K devices have six

dedicated input pins that provide low-skew signal distribution across the

device. These six inputs can be used for global clock, clear, preset, and

peripheral output-enable and clock-enable control signals. These signals

are available as control signals for all LABs and IOEs in the device. The

dedicated inputs can also be used as general-purpose data inputs because

they can feed the local interconnect of each LAB in the device.

Figure 14 shows the interconnection of adjacent LABs and EABs, with

row, column, and local interconnects, as well as the associated cascade

and carry chains. Each LAB is labeled according to its location: a letter

represents the row and a number represents the column. For example,

LAB B3 is in row B, column 3.

Table 6. ACEX 1K FastTrack Interconnect Resources

Device

Rows

Channels per

Row

Columns

Channels per

Column

EP1K10

144

EP1K30

216

EP1K50

216

EP1K100

312

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