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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT67F488 датащи(PDF) 97 Page - Holtek Semiconductor Inc |
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HT67F488 датащи(HTML) 97 Page - Holtek Semiconductor Inc |
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97 / 171 page  Rev. 1.60 97 �ove��e� ��� �016 HT67F488/HT67F489 TinyPowerTM A/D Flash MCU with LCD & EEPROM ACERH Register Bit 7 6 5 4 3 2 1 0 �a�e — — — — — — ACE9 ACE8 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit7~2 Unimplemented,readas“0” Bit1 ACE9:DefinePB5isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN9 Bit0 ACE8:DefinePE7isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN8 A/D Operation TheSTARTbitintheADCR0registerisusedtostartandresettheA/Dconverter.Whenthe microcontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversion cyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,the EOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset. ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigital converter. TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion processiscomplete.Thisbitwillbeautomaticallysetto“0”bythemicrocontrolleraftera conversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbeset intheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterrupt signalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramflowtothe associatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled, themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithas beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYSThedivisionratiovalueisdeterminedbythe ADCK2~ADCK0bitsintheADCR1register. AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0, therearesomelimitationsontheA/Dclocksourcespeedrangethatcanbeselected.Asthe recommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5μsto10μs,caremustbe takenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequency of4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/D clockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/D clockperiodwhichmayresultininaccurateA/Dconversionvalues. Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere, dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecified minimumA/DClockPeriod. |
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