STW81200 datasheet(31/58 Pages) STMICROELECTRONICS

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STW81200

Circuit description

7.11

Low-power functional modes

All the performance characteristics defined in the electrical specifications are achieved in full

current mode. The STW81200 is able to provide a set of low power functional modes which

allows control of the current consumption of the different blocks.

This feature can be helpful for those applications requiring low power consumption. The

power saving modes trade the current consumption with the phase noise performance,

and/or output level.

The current of the blocks defined in Table 9 can be set by software, and the power saved on

each block affect a specific performance as described in the same table.

7.12

LDO voltage regulators

Low drop-out (LDO) voltage regulators are integrated to provide the synthesizer with stable

supply voltages against input voltage, load and temperature variations. Five regulators are

included to ensure proper isolation among circuit blocks. These regulators are listed below

along with the target specifications for the regulated output voltage and current capability:

•

LDO_DIG (to supply the digital circuitry),

Vreg = 2.6 V, Imax = 50 mA, Vin Range: 3.0 to 5.4 V

•

LDO_REF (to supply the PLL),

Vreg = 2.6 V, Imax = 50 mA, Vin Range: 3.0 to 5.4 V

•

LDO_RF (to supply the rf blocks),

Vreg = 2.6 V, Imax = 100 mA, Vin Range: 3.0 to 5.4 V

•

LDO_VCO (to supply the low-voltage VCO sub-blocks):

Vreg = 2.6 V, Imax = 100 mA, Vin Range: 3.0 to 5.4 V

•

LDO_4V5 (to supply high-voltage sub-blocks):

Vreg = 4.5 V, 3.3 V and 2.6 V programmable, Imax = 150 mA

Vin Range: 3.0 to 5.4 V (when Vreg=2.6 V)

Vin Range: 3.6 to 5.4 V (when Vreg=3.3 V)

Vin Range: 5.0 to 5.4 V (when Vreg=4.5 V)

Proper stability and frequency response are achieved by adopting 10 µF load capacitors at

the regulated output pins. The optimal configuration is achieved by connecting a small

resistor in series with the capacitor in order to guarantee the controlled ESR required to

ensure the proper phase margin, together with the best performance in terms of noise and

PSRR. For a complete view of required connections and component values associated with

the LDO output pins, see the related PCB schematics section available from the STW81200

product page on the ST website.

Table 9. Blocks with programmable current and related performance

Block

Current Control bits

Affected Performance

VCO Core

ST4 Register bits[18:15]

VCO phase noise (offset >PLL_BW)

VCO Buffers and mux ST5 Register bits[12:11]

Phase Noise Floor (offset > ~10 MHz)

RF Dividers Core

ST5 Register bits [10:4]

Phase Noise Floor (offset > ~10 MHz)

RF output stage

ST4 Register bits [25:23]

RF output level

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