STW81200 datasheet(24/58 Pages) STMICROELECTRONICS

24 / 58 page

Circuit description

STW81200

24/58

DocID025943 Rev 7

Circuit description

7.1

Reference input stage

The reference input stage provides different modes for the reference clock signal.

Both single-ended and differential modes (LVDS, LVECPL) are supported; a crystal mode is

also provided in order to build a Pierce type crystal oscillator. Figure 29 shows the

connections required for the different configurations supported.

In single-ended and differential modes the inputs must be AC coupled as the REF_CLKP

and REF_CLKN pins are internally biased to an optimal DC operating point. The input

resistance is 100 ohms differential and the best performance for phase noise is obtained for

signals with a higher slew rate, such as a square wave.

Figure 29. Reference clock buffer configurations: single-ended (A), differential (B),

crystal mode (C)

7.2

Reference divider

The 13-bit programmable reference counter is used to divide the input reference frequency

to the desired PFD frequency. The division ratio is programmable from 1 to 8191.

The maximum allowed input frequency of the R-Counter is 200 MHz.

The reference clock can be extended up to 400 MHz enabling the divide-by-2 stage or up to

800 MHz enabling the divide-by-4 stage.

A frequency doubler is provided in order to double low reference frequencies and increase

the PFD operating frequency thus allowing an easier filtering of the out-of-band noise of the

Delta-Sigma Modulator; the doubler is introducing a noise degradation in the in-band PLL

noise thus this feature should be carefully used.

When the doubler is enabled, the maximum reference frequency is limited to 25 MHz.

REF_CLKP

REF_CLKN

REF_CLKP

REF_CLKN

REF_CLKP

REF_CLKN

100

STW81200 датащи(PDF) 24 Page - STMicroelectronics