STW81200 datasheet(26/58 Pages) STMICROELECTRONICS

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Circuit description

STW81200

26/58

DocID025943 Rev 7

The resulting VCO frequency is:

where:

FVCO is the output frequency of VCO

Fref is the input reference frequency

R is the division ratio of reference chain

N is the overall division ratio of the PLL

The implementation with programmable modulus allows the user to select easily the desired

fraction and the exact synthesized frequency without any approximation.

The MOD value can be set to very high values thus the frequency resolution of the

synthesizer can reach very fine steps (down to a few hertz).

A ‘low spur mode’ could be configured by maximizing both FRAC and MOD values, keeping

the same desired FRAC/MOD ratio, and setting the DITHERING bit to ‘1’. The drawback is a

small frequency error, equal to FPFD/(2*MOD), on the synthesized frequency which is in the

range of a few hertz, usually tolerated by most applications.

7.3.1

Fractional spurs and compensation mechanism

The fractional PLL operation generates unwanted fractional spurs around the synthesized

frequency.

The integer boundary spurs occur when the carrier frequency is close to an integer multiple

of the PFD frequency. If the frequency difference between the carrier and the N*FPFD falls

inside the PLL loop bandwidth, the integer boundary spur is unfiltered and represents the

worst case situation giving the highest spur level.

The channel spurs are generated by the delta-sigma modulator operations and depend on

its settings (they are mainly related to the MOD value). The channel spurs appear at a

frequency offset from the carrier, equal to FPFD/MOD and its harmonics, and they are not

integer boundary. If the MOD value is extremely high (close to the maximum value of 221-1)

the channel spur offset is of the order of a tenth of a Hertz and it appears as ‘granular noise’

shaped by the PLL around the carrier.

The STW81200 provides the user with three different mechanisms to compensate fractional

spurs: PFD delay mode, charge pump leakage current and down-split current. These

features should be adopted case-by-case as they give different results spur-level results

depending on setup conditions (reference clock frequency, PFD frequency, DSM setup,

VCO frequency, carrier frequency, charge pump current, VCO/charge pump supply voltage).

PFD delay mode

The STW81200 implements two programmable differentiated delay lines in the reset path of

the main flip-flop of the PFD. This allow different delay reset values to be set for VCO

divided path and reference-clock divided path, allowing an offset value to be forced on the

PFD and charge-pump characteristics, far enough from the zero in order to guarantee that

the whole circuit works in a more linear region.

FVCO

Fref

---------- N

⋅

Fref

----------

NINT

FRAC

MOD

-----------------

DITHERING

2MOD

⋅

-----------------------------------





⋅

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