STW81200 datasheet(29/58 Pages) STMICROELECTRONICS

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STW81200

Circuit description

7.7

Fast lock mode

The fast-lock feature can be enabled to trade fast settling time with spurs rejection,

performances which generally require different settings of PLL bandwidth (narrow for better

spurs rejection and wide for fast settling time).

A narrow bandwidth for lower spurs can be designed for the lock state while a wider

bandwidth can be designed for the PLL transients.

The wider bandwidth is achieved during the transient by increasing the charge pump current

and reducing accordingly the dumping resistor value of the loop filter in order to keep the

phase margin of the PLL constant. The duration of the PLL wide band mode, in terms of

number of PFD cycles, is set by programming the fast lock 13 bit counter.

7.8

Cycle slip reduction

The use of high FPFD/PLL_BW ratios may lead to an increased settling time due to cycle

slips.

A cycle slip compensation circuit is provided which automatically increases the charge

pump current for high frequency errors and restores the programmed value at the end of the

locking phase.

7.9

Voltage controlled oscillators (VCOs)

The STW81200 VCO section consists of three separate low-noise VCOs with different LC

Tanks structures to cover a wide band from 3000 MHz to 6000 MHz.

Each VCO is implemented using a structure with multiple sub-bands to keep low the VCO

sensitivity (Kvco), thus resulting in low phase noise and spurs performances.

The correct VCO and sub-band selection is automatically performed by dedicated digital

circuitry (clocked by the PFD) at every new frequency programming. The VCO calibration

starts when the ST0 Register is written.

During the selection procedure the VCTRL of the VCO is charged to a fixed reference

voltage.

Table 8. Current value vs. selection

CPSEL4

CPSEL3

CPSEL2

CPSEL1

CPSEL0

Current

Value

000

IMIN

158 µA

000

2*IMIN

316 µA

111

29*IMIN

4.58 mA

111

30*IMIN

4.74 mA

111

31*IMIN

4.9 mA

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