STW81200 datasheet(30/58 Pages) STMICROELECTRONICS

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Circuit description

STW81200

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DocID025943 Rev 7

The procedure for the VCO and sub-band selection takes approximately 11 * CALDIV PFD

cycles, where CALDIV is the division ratio of the programmable divider included in the path

between the PFD and the selection circuitry. The maximum frequency allowed for the sub-

band selection is 250 kHz and the CALDIV value must be set accordingly if the PFD

frequency is higher.

Once the correct VCO and sub-band are selected the normal PLL operations are resumed.

The VCO core can be supplied from 2.5 to 5 V. The LDO_4V5 regulator (programmable to

4.5 V, 3.3 V and 2.6 V) is used for this purpose. Furthermore, the amplitude of oscillation,

which trades current consumption for phase noise performance, is 4-bit programmable (ST4

ranges of oscillation amplitude for each available supply setting. In order to achieve the best

phase noise performance, the maximum amplitude setting is recommended.

7.10

RF output divider stage

The signal coming from the VCOs is fed to a flexible RF divider stage.

The divider ratio is programmable among different values (1, 2, 4, 8,16, 32 and 64) and

allows the selection of the desired output frequency band:

•

3.0 to 6.0 GHz (divider ratio = 1)

•

1.5 to 3.0 GHz (divider ratio = 2)

•

0.75 to 1.5 GHz (divider ratio = 4)

•

375 to 750 MHz (divider ratio = 8)

•

187.5 to 375 MHz (divider ratio = 16)

•

93.75 to 187.5 MHz (divider ratio = 32)

•

46.875 to 93.75 MHz (divider ratio = 64)

The final output stage buffer (pins RF1_OUTP, RF1_OUTN) is internally broadband

matched to 100-ohm differential (50-ohm single-ended) and it delivers up to +7 dBm of

output power on a 100-ohm differential load (+4 dBm on 50-ohm from each single-ended

output).

The final output stage buffer has a 3-bit programmable output level and can be powered

down by software and/or hardware (pin PD_RF1) while the internal PLL is locked. The

related circuitry, together with VCO and charge pump, is compatible with supply voltages

ranging from 2.5 V to 5 V. The regulator LDO_4V5, which supplies this block, can be set to

4.5 V, 3.3 V or 2.6 V. When supplied at 2.6 V, only the lowest 2 power levels are allowed

(see ST4 Register settings, RF_OUT_PWR bit)

An auxiliary output stage buffer (pins RF2_OUTP and RF2_OUTN) is available with the

same features of the main one.

The RF division ratio of this auxiliary output can be set independently from the main output

in order to increase the flexibility. Furthermore it is possible to get, on the auxiliary output, a

signal in phase or in quadrature with the main one, if the same frequency is selected on both

outputs.

The auxiliary output stage can also be powered down by software and/or hardware (pin

PD_RF2).

The output stage can be muted until the PLL achieves the lock status; this function can be

activated by software.

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